SU1453619A1 - Method and system for shaping and receiving television signal for image transmission - Google Patents

Abstract

This invention relates to the communications industry. The purpose of the invention is to reduce information loss during reproduction of a television (TV) signal. The essence of the D4nn method is to form a sync signal by modulating by the law of forming the members of the recurrent sequence, the number of which is equal to or a multiple of the number of lines of decomposition of the TV image in the transmitted frame. Then, the generated sync signal is mixed into the video signal and the received TV signal is transmitted over the communication channel, followed by the allocation of the video signal from the received TV signal and the sync signal. To implement this method, a system is used which contains on the transmitting side: a synchronous generator, a digital video source, a mixer, a linear encoder, a communication channel and a recurrent sync driver, and on the receiving side: a linear decoder, a receiver of a Digital video signal, an input unit, a computing unit , decision block, phased address counter and memory block. The goal is achieved by reducing synchronization failures. 2 sec. f-ly, 7 ill.

Description

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The invention relates to the communications industry and can be used in the construction of synchronization devices for television systems of various purposes,.

The aim of the invention is to reduce information loss during reproduction of a television signal by reducing synchronization failures.

The essence of the method lies in the fact that they generate a sync signal, which is modulated according to the law of formation of the members of the recurrent sequence, the number of which is equal to or a multiple of the number of lines in the transmitted frame. After that, the sync signal is kneaded into a video signal obtained by analyzing the image with decomposition into separate compressive elements and converting their light and color technical parameters into an electrical signal. The received television signal is then transmitted over the communication channel.

Next, a video signal and a sync signal controlling the synthesis of the image are converted from the received television signal by converting the total video signal into light and color technical parameters of the reproduced image elements.

At the same time, due to the fact that the sync signal is modulated, it is possible to determine (calculate) the number of the current member of the recurrent sequence, i.e., by receiving the sync signal, upon receiving the sync signal. determine the correct temporal position of the instantaneous current transmitted information (line) and implement the correct synthesis of the transmitted television (TV) image, without waiting for the end of the transmitted frame.

FIG. Figure 1 shows the structural electrical circuitry of the system for forming and receiving a television (TV) signal during transmission of images; FIG. 2 is a structural electrical circuit of a digital video signal receiver; in fig. 3 - structural electrical circuit of the input unit; in fig. 4 is a sequential register flowchart; figure 5 - structural diagram of the computing unit; in fig. 6 is a block diagram of a memorized unit; in fig. 7

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block diagram of the sync signal generator.

The system of formation and reception of a television signal when transmitting images contains on the transmitting side a synchronous generator 1, a source 2 of a digital video signal, a mixer 3, a linear encoder 4, a communication channel 5, a shaper of a recurrent synchronous signal 6, and on the receiving side a linear decoding device 7, a receiver 8 digital video signal, input unit 9, computing unit 10, decisive unit 11, phased address counter 12, unit

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The receiver 8 of the digital video signal (figure 2) contains a synchronous generator

14 is read, a frame memory unit 5, a digital-to-analog converter (D / A converter) 16, a display device 17.

Input unit 9 (fig.Z) contains a sequential register 18, the first 19 and second 20 shift registers.

Serial register 18 (Fig. 4) contains a random access memory (RAM) 21, D- flip-flop 22, address counter 23.

Computing unit 10 (FIG. 5) contains an adder 24, a comparator 25, a shaper 26 of a number value, a converter 27.

The memory unit 13 (FIG. 6) contains the first to the fourth RAM 28-31, the output register 32, the address counter 33.

The synchronization driver 6 (Fig. 7) contains a counter 34, a converter 35, a control counter 36, a multiplexer 37.

The system for implementing the method works as follows.

The clock generator 1 operates in the usual way and generates all the clock signals and clock pulses necessary for the operation of the source 2 of the digital video signal, the mixer 3, the linear encoder 4 and the sync signal generator. Three of these, the digital video signal source 2 operates in the usual way: a television camera controlled by the clock signals of the clock generator 1 generates an analog video signal that is converted to a digital video signal (digital stream) and is fed to the output 2 of the digital video signal.

Mixer 3, which is a multiplexer that provides mixing in a digital video signal to the first input of the mixer 3, a synchronization signal, which is connected to the second input of the mixer 3, from the output code of the recurrent signal generator 6, and the hold time (in the switched state of the mixer from the first input the second input is determined by the duration of the pulses of the rows arriving at the control input of the mixer 3 from the second output of the clock generator I. In an example of a specific implementation, the duration of the pulses of the rows arriving at the control Mixer input 3, should be equal, where T is the number of clock pulses (clock intervals).

Shaper 6 recurrent clock signal (Fig.7) works as follows

in a way. The pulses of the lines of the synchro-generator 25, the first output of the linear decoding torus 1, are fed to the counting input of the device 7, a regenerating counter 34 is formed, which is a binary counter with a counting factor, where M is the number of lines in the transmitted TV frame, and operates as follows. With the aid of frame clock pulses of the oscillator 1, the counter 34 is zeroed once per frame, i.e. At the output of the counter 34, an address signal is generated that carries information from the number transmitted. a line in a frame that is simultaneously the value of the number of a member of a recurrent sequence, expressed in binary form. Transform-to shift. In this case, the register is 18 and is length 35, built on a programmed, where o is the number of clock

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(EPROM), provides conversion of the value of the number of a member of a recurrent sequence into its specific value according to a known recurrent equation, for example, U. with and, 0 and. The algorithms and programming table of the EPROM using such a simple equation are not very complex and can be easily implemented in practice.

Control counter 36 is a binary counter with a counting factor, where T is the number of clock intervals needed to transmit the value of the recurrent sequence member. Counter 36 only works during im4

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Pervs in a row, provides a digital delay in each signal per line, i.e. the period of the sync signal in our particular implementation case. As a result, at the outputs of registers i9 and 20 with the length, where T is the number of clock intervals required for transmitting the synchronization signal, code combinations, undelayed and delayed per line, are selected and fed to the output of the input block 9. At the same time, the sequential register 18 (figure 4) works as follows. The digital video signal sends from the information input of the RAM 21, to the address inputs of which signals are sent from the address counter 23, to the counting input of which, the combined

pulses of rows of duration T, arriving at its installation input and permitting its operation during pulses of rows.

The multiplexer 37 generates a sync signal at the output by reading the information supplied to the information inputs from the converter output 35 by the control signals from the output of the control counter 36. A linear encoder 4 of a digital video signal and a clock of 1-1 pulses generates a linear code at the output, i.e. a code for transmitting digital signals over communication lines (channels).

Channel 5 communication provides transmission of a linear code from the output of the linear

0 encoder 4 to the input of the linear decoding device 7, which regenerates from the linear code the original digital video signal and clock pulses. At the same time

A digital video signal, and at the second output of a linear decoder 7, clock pulses are released that are synchronous with the regenerated digital video signal.

Input unit 9 (fig.Z) works as follows. The information input of the serial register 18 and the first register 19 receives a digital video signal, and the clock inputs of the serial register 18 receive the clock pulses of the first shift register 19 and the second register 20

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Pervs in a row, provides a digital delay in each signal per line, i.e. the period of the sync signals in our particular implementation case. As a result, at the outputs of registers i9 and 20 of length, where T is the number of clock intervals required for transmitting the clock signal, code combinations, undelayed and delayed per line, are selected and fed to the output of the input unit 9. At the same time, the serial register 18 ( 4) works as follows. The digital video signal supplies to the information input of the RAM 21, to the address inputs of which signals are sent from the address counter 23, to the counting input of which, the combined

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with INPUT Write-read RAM 21 and clock input B - flip-flop 22, clock pulses are applied. In the first half of the clock interval with a high level at the input Record-read (WE) in the RAM 21, information is read from the RAM 21 at the address H, which is determined by the state of the counter 23. In the middle of the clock interval by the difference at the clock input D -trigger 22 records information from the output of RAM 21 into it. In the second half of the clock interval, when the signal level is low, the recording input (WE) of RAM 21 records information into RAM 21. By the difference at the end of the clock interval, the state changes no counter 23 with AJ n A 2 ,, ive clock interval following process is repeated.

Computing unit 10 produces a determination of the value of the member of the recurrent sequence by the value of the previously received values of the members of the recurrent sequence according to a previously known recurrent equation. In particular, the computing unit 10 (FIG. 5), which receives a clock signal, which is encoded according to the law of forming members of a recurrent sequence of the form +1, works as follows. The first input of the adder 24 is supplied with an information signal from the output of the second register 20 of the input unit, i.e. the received value of the number U, and the second input of the adder 24 is supplied with a fixed value of the number from the imager 6 of the number value. Given that the adder 24 does the summation over the expression +, then such a fixed number is 1 or in binary form 00000001. The value of the number Uf, j. ,, calculated by the formula and, and + 1 in the adder 24, is fed to the first input of the comparator 25, the second input of which receives the information signal from the output of the first shift register 19 of the input unit 9, i.e. the accepted value U of the recurrent sequence member. If the received value U, of the member of the recurrent sequence coincides with its calculated value, then the comparator 25 generates a correspondence signal (coefficient) equal to 1 in a given time interval, and otherwise - a correspondence signal equal to 5

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0. Converter 27 provides the conversion of the value of the received Uf ,, member of the recurrent sequence into the address signal of the phased address counter 12. Note that converter 27 performs the inverse function of converter 35 (Fig. 8).

The decisive block I I at each clock interval determines (assigns) the values of the similarity coefficient depending on the value of the correspondence signal generated at the output of the compiler 25 of the computational unit 10, and on the value of the similarity coefficient delayed per line in the memory block 13.

Moreover, in accordance with the described algorithm and programming table of the EPROM, on which solving block 11 is executed, the value of the similarity coefficients increases if the signal (coefficient) corresponds to the output from

5 of the computational unit 10 is equal to 1, or falls if the signal corresponding to the output of the computational unit 10 is equal to 0. In this case, the maximum value of the similarity coefficient, equal to 1111, and the minimum value, equal to 0000, is possible. Due to the fact that the sync signals are encoded according to the formation law members of the recurrent sequence are located at well-defined clock intervals of the line, and spurious sync signals that can occur randomly in the information part of a digital video signal will not be repeated during s multiple rows at a specific line clock interval, the similarity factor value at the output deciding unit 1I will increase only to a very specific line clock interval, where the clock signal. When the maximum value of the similarity coefficient is 1111, the decisive block 11 at the second output generates a phasing signal (command) to the phased address counter 12, which operates as follows. Phased address counter 12, t-counting coefficient K, 5 о {М 2 «2 2% built on binary meters, for example integrated circuits K531IE17, and having the ability to pre-set the number, when it receives a signal

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the phasing from the second output of the decision unit 11 is transferred to the preset number mode, while the information inputs of the chip 12 are fed to the information inputs of the phasing output from the computing unit 10, i.e. in this case, the number of the last received member of the recurrent sequence U will be recorded in it, thereby phasing the counter 12 in accordance with the current phase of the received digital video signal.

The memory unit 13 (Fig. 6), which ensures the storage of the four-bit value of the similarity coefficient in each clock interval and the delay of this value per line, works as follows. The information D-inputs of RAM 28-31 receive the values of the coefficients of similarity. The clock input of the output register 32, the counting input of the address counter 33 and the write-read (WE) inputs of RAM 28-31 are clocked. At the same time, in the first half of the clock interval with a high potential at the input Write-read in RAM 28-31, information is read from RAM at address Hj, determined by the state of counter 33. In the middle of the clock interval, the differential is recorded in register 32, according to vivshey at the exit of RAM. In the second half of the clock interval, when the signal level at the input Write-read (I-Ti) of RAM 28-31 is low, information arriving at the information inputs of RAM 28-31 is recorded. By the differential at the end of the clock interval, the state of the counter 33 changes from L to A. And in the next clock interval the process repeats.

The phased address counter 12, having a counting coefficient K., built on binary counters and having the ability to preset the number, works as follows. The information inputs of the preset of the number of the phased address counter 12 are fed with address signals containing information about the number of the last member of the recurrent sequence received, and the input from the preset control of the counter 12 is given a signal from the first

output solver block 1I. In this case, the counter 12 records the number from the output of the computing unit 10 and the address output signals of the counter 12 are set to the desired phase to the clock with respect to the input received video signal. 15 frame memory of a digital video receiver 8 (FIG. 2), operating as follows. The digital video signal is fed to the information input of the 15 frame memory unit. Recording of this digital video signal is controlled by clock pulses received at the second input of digital video signal receiver 8 and, respectively, at the clock input of frame memory I5, and address signals received at address recording inputs of frame memory block 15. The read sync generator 14 generates the clock and address read signals necessary to correctly compute the digital information from the frame memory unit 15, and works in the usual way. In this case, the digital information counted from the frame memory unit 15 is fed to the digital-to-analog converter 16, where all the necessary operations are required to convert the TV information from digital to analog. The video signal in analog form from the code of the digital-to-analog converter 16 is fed to the first input of the display device 17. The sync clock signals from the second output of the sync generator 14 are fed to the sync input of the display device 17.

Claims (1)

1. A method of generating and receiving a television (TV) signal when transmitting an image, comprising generating a sync signal, zapping it into a video signal, transmitting the received TV signal via a communication channel, and then extracting the video signal and sync signal from the received TV signal, aphids, in order to reduce the loss of information when playing a TV signal by reducing synchronization failures, the sync signal is formed by modulating by law the formation of recurrent sequence members, the number of which is equal to or a multiple of the number of decomposition lines of the TV image in the transmitted frame. 2, C-system for generating and receiving a television signal when transmitting an image, containing on the transmitting side serially connected synchro generator, source I of a digital video signal, mixer, linear encoder, The second input of which is connected to the second output of the synchro-generator, and the channel: communication, and on the receiving side - a linear: decoding device, to the input of which a communication channel is connected, and a digital video signal receiver that is input to the transmitting - side recurrent sync driver, the first, second and third inputs of which are connected | second, third and fourth outputs:; sync generator, and the output of the recurrent sync signal generator is connected to the second input of the mixer, to the third input which is connected to the fourth output of the synchronizing generator, and at the receiving side a memory block and a serially connected input block are inserted, the first output of the linear decoder, the computing block, the decisive block, the second input of which is connected to the memory block, and an address-counter, the output of which is connected to the address input of the digital video signal receiver, to the clock input of which the clock input of the memory unit is connected, the clock input of the phased address Meters withstand, a clock input and a second input unit VEHOD linear decoder, the data input to the address counter connected faziruemogo second output computing unit, and to the data input of the memory unit is connected the second output of the block casting. (4idarovoi {ideihigial Toff / nofbie UftnyA C I Clock entrance (dyrmaicon inlet9 nineteen Value number | 7 Value auxoi Fig.d 15 ffflecm / e CUfftOAbI FIG. g 20 Fiyo.5