SU1453549A1 - Method of controlling transistor gate - Google Patents

Abstract

The invention relates to converter equipment and can be used, for example, in secondary power sources. The aim of the invention is to expand the allowable range of variation of the parameters of the key transistor and the load. The purpose of the invention is achieved due to the fact that when the parameters of a transistor or load change, the base current is controlled by the locking voltage depending on the time delay of the current dropping time relative to the time of the control current dropping. In this case, the blocking voltage is formed in the form of pulses whose duration is equal to the aforementioned delay time. This control method allows for changing the load or the parameters of the transistor to work out the desired output pulse duration with higher accuracy. 3 il. o (l

Description

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The invention relates to a conversion technique, in particular, to controlling transistor switches, constructed using substantially powerful high-voltage bipolar transistors. It can be used in electric drives, transistor inverters, powerful secondary power sources with transformerless input and other devices.

The purpose of the invention is to expand the permissible range of variation of the parameters of the transistor and the load.

FIG. 1 and 2 shows the variants of the device that implements the proposed method; in fig. 3 - timing diagrams explaining the method.

The device (Fig. 1) for controlling the transistor 1, the collector-emitter junction of which through the current sensor 2 is connected to the output terminals 3 and 4 of the transistor switch, which also has input terminals 5 and 6, contains an amplifier 7, through which The base-emitter junction of transistor 1 is connected to voltage source 8. The output of current sensor 2 through differentiating element 9, containing in the simplest case a capacitor and a resistor, is connected to the input of comparator Yu, which is a unit of comparison with an internal source of reference voltage. Comparator output

10 is connected to the first input of the element 11, the second input of which is connected to the input terminal 5. It is last connected via the start circuit 12 to the control input 13 of the amplifier 7. You are running the element 11 and are also connected to the control input 13 of the amplifier 7. increasing the reliability of the output of the comparator 10 can be connected to the first input of the element 11 through the impulse duration driver 14.

The device shown in FIG. 2, in contrast to the first, as a current sensor 2, a current transformer which simultaneously performs the function of a differentiating element.

The diagrams (Fig. 3) show: a - the control voltage voltage supplied to the input terminals 5 and 6, b - the key load current, which varies from the maximum to the minimum value during the open

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key state}. в is the base current of the transistor 1i g is the voltage at the input of the comparator J d is the voltage at the output of the comparator; e is the voltage at the control input 13 of the amplifier 7, where the trigger voltage pulses are normalized in duration (with the exception of the first, the duration of which defines the start circuit 12).

The device (Fig. 1) works as follows.

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At the moment when unlocking voltage is applied to terminals 5 and 6, the starting circuit shunts the AND element for a while. The starting circuit 12 may be formed by a capacitor, then the indicated time is determined by its charging time. Thus, the first impulse of the voltage is supplied to the input 13 of the amplifier 7, while the power transistor 1 is also unlocked. After the end of the first pulse of the base current, the transistor 1 remains open for some time due to the excess charge accumulated in its base for time of the first base current pulse. As the excess charge dissolves in the base of transistor 1, the collector-emitter junction resistance begins to increase, the load current decreases. In this scheme, the moment of the output of the transistor and saturation (it is also the moment of applying the next pulse of the base current) is determined by the achievement of the decay rate of the key load current of some given value. The rate of change of the load current is varied by means of a differentiator and a comparator. When the voltage at the output of the link 9 of the comparator setpoint, the output voltage appears at the output of the latter, unlocking the amplifier 7, while the base current of the base current is applied to the base of the transistor 1, leading to an increase in the load current to the previous value. The duration of the pulsing voltage pulses is normalized by the shaper 14. When the load decreases, the absorption time of the excess charge carriers in the base of transistor 1 increases, since the amplitude and duration of the base current pulses are unchanged, i.e. the interval between these pulses increases.

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The operation of the device shown in FIG. 2, analogs1 occur; but.

The proposed method of controlling the transistor switch is performed as follows. During the time interval between the pulses of the unlocking base current at the input 13 of the amplifier, a zero (blocking) voltage is generated, the duration of which is equal to the time delay of the decay moment of the force current (load current ) key in relation to the moment

decay base current. Moment of completion

The application of a blocking voltage (the same time as the next pulse of the base current is applied) is determined by achieving the derivative of the load current of the comparator setpoint.

The duration of the locking pulses here is close to the time of dissipation of excess charge from the base of the power transistor under these conditions, i.e. at a given amplitude and duration of the base current, and also considering that the next base current pulse is applied at the moment when the transistor is already depressed. If the pulse duration is set sufficiently short, then, under these conditions, the pause between the base current pulses is significantly less than the transistor dissipation time for the same load current, even if the amplitude of its base current is corrected (in the case of a continuous base current). There is also a limit on the minimum duration of the base current pulse.

because it should be sufficient to create some minimum saturation.

Since the error of testing the specified duration of the control signal is equal to the duration of the pulse voltage pulse (pause between

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base current pulses), with an appropriate choice of the base current pulse parameters, it may be less than for the case of analogue base current control.

In practical devices, for a given load range, the duration of the base current pulses can be set two to three orders of magnitude lower than the minimum control voltage duration at the input terminals 6 and 5 of the switch. The duration of the locking pulses of the same order.

Thus, the proposed method allows you to quickly adjust the base current to the load current, and the error of testing the specified duration of the control signal does not exceed 0.1-1%, which is sufficient in most practical cases.

Claims (1)

Invention Formula The method of controlling a transistor switch, which consists in measuring the time delay of the decay of the power current of the transistor switch relative to the time of the control current dropping, forms the blocking voltage of the transistor switch depending on the specified delay time and when the parameters of the transistor switch or load change the base of the key transistor is varied in proportion to the blocking voltage, hence - so that, in order to expand the allowable range of the transistor parameter and load, irayuschee voltage of the transistor switch is formed as a voltage pulse whose duration is equal to the delay time of the time decay of power transistor switch current with respect to time the downslope control. 6 1 3 It FIG. 2 pppp p Fig.Z