SU1444803A1 - System for processing unclear information - Google Patents

Abstract

The invention relates to computing and can be used to create devices for processing fuzzy information in artificial intelligence systems for creating devices for parallel processing of data streams. The aim of the invention is to improve the speed when processing fuzzy operands. The fuzzy information processing system contains the register, commands, descrambler, firmware control block, feature register, instruction address counter, RAM, ALU, switches, registers, operand bus drivers, AND group, address switch, switch control unit, bus driver control unit operands, current keys, transfer control block. New in the device is the possibility of not only parallel processing of multiple operands, but also sequential processing, and with dynamic changes in the size and number of data streams. 2 hp f-ly, 6 ill. W (L with

Description

four

four::

00

  one

The invention relates to computing and can be used to create devices for processing fuzzy information in artificial intelligence systems, to create devices for parallel processing of data streams.

The aim of the invention is to improve the speed when processing fuzzy operands.

FIG. 1 is a block diagram of a system for processing fuzzy information; FIG. 2-4 are block diagrams of control units for bus operand- ing, transfer control, and microprogram control units, respectively; Fig. 5 is a timing diagram of the operation of the firmware control unit; in fig. 6 is a schematic diagram of the switch control block.

The processing system of fuzzy information (Fig.) Contains a register of 1 commands, a decoder 2, a microprogram control unit 3, a register of 4 features, a command address counter 5, a random access memory (RAM) 6 and arithmetic logic units (ALU) 7 , n switches 8, n registers 9, 2 n bus drivers of operands 10, a group of n-1 elements 11, switch 12 addresses, switch control block 13, block 14 of control forwarders of operands, three current switches 15-17 and block 18 transfer controls.

The bus driver control unit 14 (Fig. 2) contains three decoders 19-21, a group of n elements OR 22, three AND elements 23-25 .. and three elements NOT 26-28.

The transfer control unit 18 (FIG. 3) contains two .I elements.

29-30 and two elements NOT 31, 32.

Microprogram control unit 3 (Fig. 4) contains a microcommand address switch 33, microcommand address counter 34, memory 35, microcommand register 36, switch 37, trigger 38, generator 39, five items 40-40, two HE elements 45 ,four

The switch control unit 13 (FIG. 6) contains three decoders 47 49, three elements NOT 50-52, three elements AND-53-55 a group of elements OR 56 and an element OR 57.

The algorithm of the system for processing fuzzy information in general form is as follows.

The system is designed to perform logical and arithmetic commands on single clear numbers and in parallel on sets of clear numbers and fuzzy numbers. A fuzzy number is understood to be the set, in A {ji, ft (X), X, where | Uft, l is the map of the set into a single segment, lj, and is called the membership function of the fuzzy set A. The value of the membership function | Uft (X) for the element is called the degree of credibility. The interpretation of the degree of belonging is a subjective measure of how far an element x Х X corresponds to a concept whose meaning is formalized by a fuzzy set A.

As an example, consider

a clear set A, corresponding, within a specific problem, to a fuzzy number 2:. AJ 0.05 / 1.7; 0.5 / 1.8; 0.8 / 1.9; 1/20 0.8 / 2.1; 0.5 / 2.2; 0.05 / 2.3}. Logical operations on operands are defined as A to B C,

in - the result of the logical intersection operation (A)

Consider performing a logical join operation.

Let given a fuzzy operand A (a, | C, ..., a, | C) and a fuzzy operand B (b, | U,..., B „| 11), then in accordance with formula (1) and assuming operands are given on the whole area

five

definitions

those.

 B and

 B,

 ti t

(if this is not the case, then one of the operands can be extended by the values with the function, membership equal to zero), we write:

U448034

inax (p, ju), a, ;; raax (| U, | li2), ... max ((t, | u) a „.

Thus, the logical function Consider performing the operation of combining the fuzzy operands of the preposition. Let an odd set be a multiply element by element max function A (a, ii, ...., A „| U) and nothing (by belonging on the whole domain, the set B (b, t%. .., b / C) definitions of fuzzy operands.

Arithmetic operations under fuzzy numbers are defined as

lack of boldness

then, in accordance with formula (2), Q for each pair of values from the domain of definition of fuzzy sets, we write:

С max (min (| u1 (U), a; x bj (2)

Consider performing an add operation. Let an odd set A (a, ii, ...., A „| U) and not (the set B (b, t%. .., bn / c),

lack of boldness

then, in accordance with formula (2) Q, for each pair of values from the domain of definition of fuzzy sets, we write:

min () a, + b,; min () a, b j ... min () a, + b,

min () ar + b,; ju) a., +, ... min (| u5 / U,} a. + b (3) t1n (| 1 ((U) a, + b,; min (| u1, (Uj) a + b ; ... t1n () a „+ b„

Suppose that all the fuzzy operands involved in an operation are specified, a, -a.

a „a, b, -b,

This requirement is doable, because interstitial values in the set, if & A 5, then a fuzzy set with a smaller step, the property given with a big step, then, based on the expression (4)

but to define or discard the pro-zo by analyzing the matrix (3) - we have:

a + b, (a, + d) b, a, + (b, + ft)

B, a + bg a, + b

+ B, a

j + ba-a + bz - a, t and,

+ B.

Modify the matrix (3) so that in one column the values of the desired fuzzy set are found, 40

max

of the desired fuzzy set C, respectively, at the point:

In accordance with formula (2), the maxima taken in the columns of the matrix (5) will give the value of the function belonging to

(a, + b,), (a, + b), ..., (a, + b), (a2 + b), (a, + b) ().

The algorithm for performing arithmetic is developed on the basis of expressive operations of addition and subtraction, marriage (5). which implements the submitted mouth

on the definition area with the same step i, i.e.

Bs - b

L – L „.,. (four)

a, + b,

3

t and,

+ B.

related to the same domain of definition, i.e.

min

(

I

max

of the desired fuzzy set C, respectively, at the point:

First, a parallel search is performed for min in rows, respectively, for n commands, and then for n commands, parallel operations are performed between rows with the result shifted to the left by one value of the membership function after each max operation. The described algorithm allows for the arithmetic operations of addition and subtraction of fuzzy sets, and not only by parallel processing commands for sets, but also by sequential commands, processing 4-J 8- and 1 6-bit operands.

Consider the operation of this device on the example of the execution of the command for parallel processing of multiple operands. Let this command be in register 1 of commands. The operation code of the command and the parallel processing flag are transmitted through the decoder 2 to the firmware control unit 3, in which either the address of the microcommand is written or one is added to the address, i.e. Two of the control signals are produced, the recording signal in the registers 9.1,.,., 9, n and the recording in the register of 4 signs, strobing with a clock frequency, which makes it possible to form a recording strobe in sequential micro instructions.

The control signals of the microcommand configure the address switch 12 so that the address of the first operand arrives at the second input of the random access memory 6, the first input of which receives the code specifying the read mode. As a result, in the first 4 outputs of the random access memory 6 a read word appears. Each of the n outputs is four-bit, so the word width is 4xp. Read word enters the second inputs of the ALU 7.1 ,. .., 7.n, which are controlled by the control signal V5 to skip the operand from the second. the input to the output without change. Next, the operand through the switches 8.1 ,. . ., 8.p on the leading edge of the control signal, the U6 is written to registers 9.1, ..., 9.p. This completes the filling of the first microcommand.

In block I3 control switches in this mode to the input of the formation of the code from the field of microcommand on

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step sign of sequential processing of operands, since we consider the command parallel (- processing, then this sign is zero.

In the single state, it appears in the field of the microcommand only if necessary to generate at outputs 10 dah 1, ..., n the block 13 of the control of the switches of code 11, according to which the switches 8.1 ,,,, 8. can adjust to skip the information of the ALU 7.1 , ..., 7.P without change.

15 When filling parallel max / / min operations at the outputs of the switch control unit 13,

O code, by which switches 8.1, ..., 8.n are configured to pass

information from the output of the operational storage device. When forming at the outputs of the block 13 of control of switches of code 00, switches 8.1, ... 8.P pass information of ALU

with a number of one large, i.e. information is shifted by four bits to the left.

Each ALU generates an output signal equal to 1 when executing operation А-В-1, if operand В A.

Thus, if the operand stored at H1-1MY in registers 9.1. ,,,. 9.p and arriving at the inputs of the second operand (inputs C) ALU 7.1, ... 7.p is larger than the operand ,, arriving at the second the inputs of the first operand of the ALU from the operative storage device 6 (the comparison is made by each other), then recording of information in the registers 9.1, ... 9.p.

Further, in the second micro-command, the second part of the address of the second operand

is read from the register of 1 commands and through the switch 12 addresses are fed to the address input of the random access memory 6. The second operand on the control signal Read (Y4) is read from the RAM and goes to the inputs of the ALU 7 .1, .-. . , 7. N, the ALU execute the commands specified by the operation code, and at their outputs the result appears that through the switches 8.1, ... 8. n is fed to the input of registers 9.1, ..., 9. n and on the front the edge of the control signal, record U6, is written to the registers.

operands vary depending on which tetrads of the ALU are allowed transfers.

The transport control block I8 analyzes the upper half of the operand address field in the instruction. If the highest bit is zero, the control unit 18 forms, at outputs 1,2,3, codes 000 which, through elements 11.1, ..., 1I.n, prohibit transfers between all ALUs, i.e. n 4-bit data streams are generated. If the most significant bit of the first part of the address is one and the second is zero, then the transfer control unit 18 generates a code 100 at outputs I, 2 and 3, which allows transfer between pairs of ALUs.

Thus, n / 2 8-bit streams are formed, i.e. There is an opportunity from the command field to control the structure of the data being processed.

In the next, third microcommand, the result of the operation is recorded at the address of one of the operands in the random access memory 6. Thus, the command of parallel processing of n-bit words is executed for three micro-commands of the bla.

The device performs two more types of parallel operations: shear and max / / min. Shift type operations differ from the execution of the described command in that in any of the microcommands the result of the operation from the output of the ALU is sent to the switch with the number one less than the number of the ALU, i.e. cyclically shifting left by four digits.

The max / min operations are different from the execution of the first command described by the fact that a comparison function is applied to the ALU from the field of the microcommand. One operand, read from the RAM, is fed to the inputs of the first operand (A) of the ALU 7.1, ..., 7.n. the inputs of the second operand (B) are given another operand, read into registers 9.1, ...,

9.P in the first microinstruction. ALU 7.1, ..., 50 operands for the entire highway.

7.P a comparison signal is generated that goes to the inputs of registers 9.1, ..., 9.n and blocks the record if the operand is C g A. Otherwise, the record will not be locked. The switch control unit 13 generates code 01, which configures the switches 8.1, ..., 8.p to skip the RAM information. So in registers

from 2 operands. In the third microcommand, the result of the operation can be

loaded into random access memory 6. Operation min executes in the same way, but only with inverse operands.

Consider the operation of the device when

sequential processing of 4, 8, and 16-bit operands.

Let a command be loaded into register 1 of commands, in the second field of which there is a sign of sequential processing, and both address parts are specified in address fields, i.e. in the first part of the address, the operand width and the block number (conditional division of memory depending on the bit size) of RAM are specified, in which it is located, and in the second part of the address, the location of the operand in the block is specified.

In the first micro-command, the second part of the address of the first operand enters the input of the switch 12 of the address and from its output to the input of the RAM 6. The control signal 14 reads the information from the RAM 6 into the ALU blocks 7.1, ... 7.n, which are configured

control signal V5 to skip information without modification. The first part of the address of the first operand enters the information management unit 14 of the bus driver, in which the three most significant bits of the address are analyzed. If the high bit is O, this means that 4-bit operands are processed. If the first bit is 1, and the second is O,

this is processed by 8-bit operands. If the first and second bits are I, and the third is O, this means that 16-bit operands are processed.

The transfer control unit 18, receiving the first three bits of the first part of the address, generates a control code for the current keys 15, 16, 17, which are necessary for reproduction

Thus, the read operand arrives at the inputs of all switches 8.1, ..., 8.n (for each pair of 4-bit switches the same 55 eight-bit operand).

Block 13 control switch-. Mi analyzes the first part of the address of the second operand. Sign of sequential processing coming from

FIELD microcommands to the input of the switch control unit 13, allows the analysis of the three most significant bits of the first part of the address. The analysis procedure is similar to that described in block 14 of the control of tire formers. As a result of the analysis, at the outputs of the corresponding pair of elements OR 56 ,, 56, n logical units appear. As a result of the analysis, code 10 is formed at the outputs 1 ,,,,, n of the switch control unit 13, on all

the remaining outputs will be code 00, Having received these control codes, all switches 8,1 ,,,, 8, n pass to. output information received from the output of the neighboring ALU, and only the selected pair of switches passes information from the trunk. Thus, as a result of executing the first micro-command, the first operand is loaded into those of registers 9.1 ,,,., 9, n, in which the second operand is read,

In the second microcommand, the word 4p is read from RAM 6 and enters ALU 7.1 ,,,, 7, p, and also to switches 8.1, ,,,, 8, p,

In the read word there will be a byte, which is the second operand, it is fed to the input of the corresponding pair of ALUs,

The ADU performs the operation determined by the control signal U5, supplied from the firmware control block.

Thus, the switches 8,1 ,,,,, n, depending on the code generated by block 13, skip the result of the operation of a certain pair of switches. The second microcommand from control unit 13, the fuzzy processing system and 30 formations, containing the command decoder register, the register of attributes, the instruction address counter, the microprogrammed control unit, the first arithmetic logic unit and the operational memory, etc. the output of the operation code of the register ka mand is connected to the input of the decoder the output of which is connected to the first I input of the microprogrammed control unit 40, the first one whose output is connected to the input of the register entry, the output of which connected to the second input of the firmware control unit, the third input of which is

 3 of the firmware control is connected to the Start system input, the signals that are generated at outputs 1 ,,,., n block 13 are code 01, through which the switches 8,1,. ,,, 8, n pass the read word. Only for two switches, whose numbers define the first gg the fourth and fifth outputs of which

The inputs of the register of command registers and the counting of command addresses are connected respectively to the second and third outputs of the firmware control block.

The second part of the address of the second operand will generate code 11, according to which the result of the operation passes through the switch and is loaded by the write signal into a pair of registers from 9.1.

The switch control unit 13 in the same command forms on one of the outputs ((n + 1) ,,,,, 2p) a signal from

ten

44480310

covering one of the bus formers of operands 10, p + 1,.,., 10.2 p, which pass the logical conditions of the operation in the ALU to the input of the register 4 from the signs, According to the signal U1, coming from the microprogram control unit 3, the conditions are written by SI in the register of 4 signs. Proceed further to the input of the microprogram control unit 3, they can be used for. organization of branches in programs.

In the next third microcommand, information from registers 9 ,,,., 9, p is written into RAM in the second part of the address of the second operand.

Despite the fact that the whole 4n-bit word was read and written, the command execution procedure described allowed modifying only one byte,

 Similarly to the considered procedure, the sequential processing of 4- and 16-bit ops is carried out.

15

20

25

Claims (1)

Invention Formula 1, The fuzzy information processing system, containing the decoder command register, feature register, command address counter, microprogram control unit, the first arithmetic logic unit and the operational memory, the output of the command register operation code being connected to the decoder input, the output of which is connected to the first I input of a laziness microprocess control block 40, the first one, the output of which is connected to the input of the record of the register of attributes, the output of which is connected to the second input of the microprogram control block audio, the third input of which so45 unified with an input system start, gg fourth and fifth outputs which one with the system start input, the fourth and fifth outputs of which The inputs of the register of the command register and the counter of the command address are connected respectively to the second and third outputs of the firmware control block. They are connected respectively to the read input of the operative memory and the enable input of the first arithmetic logging device 55, which is so that, in order to improve the speed in processing fuzzy one rand, n registers, n switches are entered into it, n-1 elements And,  . 2n bus drivers for operands, p-1 arithmetic logic units, three current switches, an address switch, a switch control unit, a bus operand control block, and a transfer control block, the address input of the random access memory connected to the address switch output, the control input which is connected to the sixth output of the firmware control block, the fifth output of which is connected to the work enable input of the i-ro arithmetic logic unit (i 2, ..., p), the input of the first operand j- The ro arithmetic logic unit (J, .., p) is connected to the jth output of the random access memory and the first information input of the j-ro switch whose second information input is connected to the first output of the j-ro result and the arithmetic logic unit. the j-ro input of the bus driver operands, the control input of which is connected respectively to the j-th output of the control unit The bus drivers of operands, the first, second, third and fourth inputs of which are connected to the outputs of the corresponding bits et al sa of the command register, and the fifth input with the output of the flag of sequential processing of the command register operands, the output of the address field of which is connected to the first information input of the address switch, the second information input of which is connected to the output of the command address counter, the reset input of which is connected to the Reset input the system and the fourth input of the microprogram control unit, the fifth input of which is connected to the transfer output of the nth arithmetic logic unit, the kth information input of the operational storage device The properties (k 3, ... 5P + 2) are connected respectively to the input of the second operand j-ro of the arithmetic logic unit and the output of the j-ro register, whose information input is connected to the output of the j-ro switch, the third information input of the th switch (t 1, ..., n-1) is connected respectively to the first output of the result (t + 1) -th arithmetic logic unit, the third information input of the n-th switch is connected to 12 0 15 4803 20 25 the first code of the result of the first arithmetic logic unit, the transfer output of the tth arithmetic logic unit is connected respectively to the first input of the mth element I, the output of which is connected respectively to the transfer input (mt-1) of the arithmetic logic unit, the second output the result of the j-ro arithmetic logic unit is connected respectively to the information input of the 1st bus driver of operands (1 n +, ..., 2n), the output of the comparison attribute j-ro arithmetic logic unit is connected respectively to the input write lock register j-ro, the write enable input of which is connected to the sixth output of the firmware control block, the seventh output of which is connected to the first and second inputs of the code generation of the switch control unit, the third input of the code generation of which is connected to the output of the command sequential processing attribute, jth output the switch control unit is connected to the control input jro of the switch, the fourth information input of which is connected to the output of the j-bus operand generator, the 1st stroke control unit the switches are connected respectively to the control input of the 1st bus driver of operands, the outputs of the 1 bus driver of operands are combined and connected to the information input of the register of attributes, the address input of the control unit the switches are connected to the outputs of the corresponding bits of the address of the command register, the outputs of the three higher bits of the address of which are connected respectively to the inputs of the three higher bits of the address of the transfer control unit, the first output of the control code of which is connected to the control inputs of the first and second current keys entrance entrance The third current key is connected to the second output of the control code of the transfer control unit, the first, second and third outputs of which are connected respectively to the second inputs dami from first to (p-1) -and elements And, with the third inputs 2p-x (p 1, 2, ...) elements And, and with a quarter input 4p-x elements And, the output of each (4j-3) - ro tire former The operands are connected respectively with the first input-output of the first current key, the first inputs of the command address counter and address register, the second inputs of which are connected respectively with the first input-output of the second current key and each output (4j-2) -ro bus driver operands, the output (4j-l) -ro bus driver operands is connected respectively to the second input-output of the first TOKOBorjo key, the first input-code of the second current key and the third inputs of the command address counter and command register whose fourth inputs connected respectively with the second inputs-outputs of the second and third current switches and the output of each contains three elements NOT, three AND elements, three decoders and a group of n OR elements, the first input of the block connected to the input of the first element NOT and the first inputs of the first and second elements AND, the second inputs of which are connected to the first input of the third element AND the second input of the block, the second input of which is connected to the input of the second element NOT, the third input of the second element AND and the first information input of the first decoder, the second information input of which is connected to the first information inputs of the second and third descriptor Hur and fourth input unit, a third input coupled to the input element of the third NOR-ro vto4j shaper operand bus. 20 by the information input of the second de. 2, the system under item 1, distinguishing the y-encoder and the third information so that the input control unit of the first decoder, the sync-transfer contains two elements AND, and the input is connected to the output two elements NOT the input of the first high-order bit of the block address is connected to the input of the first element NOT, the first input of the first element I and the first output of the block, the second output of which is connected to the input of the second element NOT, the first input of the second element 30 of the third decoder of the connection ment and and out The house of the first element And, is not with the output of the second element And, the fourth element And, the second input of which is connected to the output of the first element NOT, the output of the second element is NOT connected to the third input of the first element And, the output of which is connected to the sync input of the second decoder, the second of which connected to the input of the higher bit of the block address, the input of the third most significant bit of the address of which is connected to the second input of the second element I, the output of which is connected to the third output of the block, the first and second outputs of the control code of which connected to the outputs of the second and first tov. 3. The system according to claim 1, 1 and 2, so that the control unit of the bus formers of group 45 operands are the outputs of the block, contains three elements NOT, three AND elements, three decoders and a group of n OR elements, the first input of the block connected to the input of the first element NOT and the first inputs of the first and second elements AND, the second inputs of which are connected to the first input of the third element AND the second input of the block, the second input of which is connected to the input of the second element NOT, the third input of the second element AND and the first information input of the first decoder, the second information input of which is connected to the first information inputs of the second and third decoder The fourth input of the block, the third input of which is connected to the input of the third element NOT, the second decoder and the third information input of the first decoder, the sync input of which is connected to the output of the third decoder's input, connects the second element I, the second input of which connected to the output of the first element NOT, the output of the second element is NOT connected to the third input of the first element I, the output of which is connected to the sync input of the second decoder, the blue input of which is connected to the output of the third lementa NOT, j-th output of the first decoder is connected to a first input of the j-ro of the OR gate groups, respectively (1, ..., n), the second inputs of OR group elements are pairwise combined and connected respectively to the i-M output of the second decoder and (i 1, ..., p / 2), the third inputs of the elements of the OR group are combined in a tetrad and connected respectively to the k-th output of the third decoder (k 1, ..., p / 4), the outputs of the elements 1 Shi  I Y / ys 1 g / WA razr. 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