SU1442946A1 - Apparatus for testing monitoring devices - Google Patents

Abstract

The invention is intended to verify the parameters of seed monitoring devices. The purpose of the invention is to expand the functionality. The device provides control of the threshold frequency of the devices being tested. At the output of the logical switch, a pulsed test signal is formed, the period of which is automatically increased linearly. At the time of actuation of the device under test 5, the synchronization unit 14 stops changing the test signal period. The threshold frequency value is determined by the first block 18 of indicators, to which the contents of the counter 12, which forms the follow-up period of the test signal, are output. The number of the channel to be tested is determined by the second block 6 of the indicators, indicating the state of the logical switch 1. The device generates a warning signal when the device under test 5 fails. 1 sludge. S cl

Description

4ib 4

to

CO 4

ABOUT)

The invention relates to monitoring devices and is intended, in particular, to verify the parameters of seed monitoring instruments.

The purpose of the invention is to expand the functionality.

The drawing shows a functional diagram of the device for testing control devices.

A device for checking control devices contains a logical switch 1, made on a distributor of 2 pulses, to each of which. The inputs of the elements AND-OR 3, - ZG, are connected. The outputs of these elements are the output terminals 4, -4 "of the device and serve to connect the inputs of the device under test 5. In addition, the outputs of the distributor 2 are connected to the inputs of the indicator block 6, indicating the status of the distributor 2. The control inputs of the switch 1 are connected a control unit 7, composed of shapers 8 and 9 of single pulses, made, for example, on single-vibrators, and two buttons; button 10 Checking the device and button 11 Setting the initial position. Inputs sc. The 12 and 13 pulses are connected to the outputs of the synchronization unit 14, the inputs of which are connected to the outputs of the block 7, the output of the clock generator 15 and the output of the bit-comparison unit 16. The inputs of block 16 are connected to the outputs of counters 12 and 13. The output inputs (inputs 1 tr) of the first counter 12 are connected to the outputs of the former G / parallel code of the number N, and the outputs of the counter 12 to the inputs of an additional block 18 of indicators. The synchronization unit 14 contains the elements OR 19 ch 20, the elements 21 and 22 and the triggers 23 and 24.

The output of the block 16 is connected to the first input (bus 26) of the switch 1 via a pulse expander 25, for example, on the one-vibrator. The output of the clock generator 15 is connected to the second input (bus 28) of the switch 1 via the frequency divider 27 via the bus 28 (output 28). the transfer (output P) of the counter 12 is connected by bus 29 to the synchronization unit 14, and the output is checked on the gear of the device 5 connected to the input of the same unit by the bus 30,

five

0

five

0

five

0

five

0

five

The device works as follows. in a way.

Before starting the instrument check, the circuit is reset to the initial position by pressing a button. eleven . In this case, the former 9 generates a single pulse, with which the distributor 2 is set to the zero position. At the same time, on the block 6 of the indicators, zeros are highlighted, and on the outputs from the 1st to the 5th, logical zeros are set in the distributor 2, allowing the pulses from the output of the divider 27 to pass to the inputs of the tested device 5. The parameters of the divider 27 and the clock generator 15 are selected so that the frequency of the pulses arriving at the inputs of the checked channels of the device 5 corresponds to the nominal seeding mode. In this case, the device 5 does not generate a warning signal and the level of logical zero is maintained on the bus 30. In addition, the output pulse of the imager 9: the trigger 23 is set to zero zero, which prevents the passage of pulses through the element 21 to the input of the counter 13.

To start the test, press the button 10 Test instrument. In this case, the output pulse of the generator 8 and the distributor 2 is set to a single state, in which the logical output of the lower circuit of AND 3 and the preparation of the upper circuit AND of element 3 is established at the first output of the distributor 2 to transmit pulses from the output of the expander 25 to the input of the first the channel of the device under test 5. In this case, on the block 6 of the indicators the number of the channel under test is displayed. In addition, a single pulse from the output of the imaging unit 8 acts through the synchronization unit 14 on the inputs of the counters 12 and 13 and performs the following preparatory operations: through the OR element 19 it sets the counter 13 to the zero state; through the element OR 20, writes into the counter 12 the number N, coming from the output of the former 17 of the parallel code to the bit inputs (input P, T),. .., DB,) counter 12; sets trigger 24 to the unit state, thereby preparing the K 22 element to pass Igggles to the counting

input (input from) counter 12; Sets the trigger 23 to a single state, thereby connecting the output of the clock generator 15 through the AND 21 element to the counting input of the counter 13, which starts the counting of pulses.

When the counter 13 receives N clock pulses, the numbers recorded

is related to the number q recorded on the counter 12, by the relation f „1 / (a T).

In case the device 5 is faulty and a warning signal is not generated, the counter 1 2 overflows and the transfer pulse over the bus 29 into the counter 12 again records the number N, after which the repeated

15

20

thirty

in counters 12 and 13, the equal check of the same channel becomes equal. By the appearance of a parallel comparison at the output of the block 16, a pulse is formed, which through the element OR 19 the counter 13 is set to the zero state, and the contents of the counter 12 by the same pulse GW are increased by one, i.e. it sets the number (N + 1), which is highlighted by an additional indicator of block 18. In addition, the pulse from the output of block 16, extended by the expander 25 to the required start, goes to the test device through element 3 ,, and clip 4.

After that, the counter 13 again enters the clock counting mode. When (N + 1) clocks arrive at counter 13, a pulse is formed again at the output of block 16, zeroing counter 13 and increasing the contents of counter 12 by one. At the same time, the second pulse from the expander 25 output to the input of the first channel of the device 5 is separated from the beginning of the first pulse by time T, (N + 1) T, where T is the period of the clock pulses.

Further, the processes of zeroing the counter 13 and increasing the number N are repeated cyclically in the same way, as a result of which the pulse duration at the input of the first channel of the device 5 in each cycle increases by T, which is equivalent to lowering the pulse frequency at the output of element 3 . As soon as the frequency of the pulses at the input of the tested channel becomes equal to the threshold frequency at which device 5 is triggered, a warning signal is generated by the device being tested 5, and on bus 30 a logical unit appears that the trigger 24 is set to the zero state. As a consequence, the element I.22 stops passing pulses to the counting input of the counter 12 and its contents remain unchanged. According to the indications of the indicator of the transfer pulse unit 18, a failure is detected of the tested channel of the device 5,. (Fault indicator not shown). After completing the verification of the first channel, press the button 10 and proceed to the verification of the second channel, at the output 2 of the distributor 2 a logical one appears and at the output 1 a logical zero. As a result, the output of the expander 25 pulses is connected to the input of the rotor channel of the device 5, and the inputs of the remaining;; output channels of the device 5 are connected to the output of the pulse divider 27 pulses. 25 The second channel is checked in the same way.

Pressing the button 10 successively, check all channels in the described manner and determine the threshold frequency of each channel of the device 5 according to the indications on the indicator of block 18. At the same time, the number of the channel being tested is displayed on the indicator of block 6.

35

After checking all the channels of the device 5, the button 11 is pressed and the device is set, and on block 6 zeros are written to carry the devices to the socket.

In the initial state, the indicators will indicate a ready-to-carry pro45

50

55

Claims (1)

Invention Formula A device for testing control devices, comprising a logic switch connected to an indicator unit, a control unit, the outputs of which are connected to the control inputs of the logic switch, and a clock generator, characterized in that, in order to expand the functionality, two pulse counters are inserted into it, bit comparison unit, additional indicator block, pulse spreader, code generator, frequency divider and synchronization block,  divide the threshold frequency f of the tested channel of the control device 5, which check the same channel. By appearance of the impulse of transfer, about the fault of the tested channel of the device 5,. (Fault indicator not shown). After completing the verification of the first channel, press the button 10 and proceed to the verification of the second channel, at the output 2 of the distributor 2 a logical one appears and at the output 1 a logical zero. As a result, the output of the expander 25 pulses is connected to the input of the rotor channel of the device 5, and the inputs of the remaining;; output channels of the device 5 are connected to the output of the pulse divider 27 pulses. The verification of the second channel is carried out in a similar manner. Pressing the button 10 successively, check all channels in the described manner and determine the threshold frequency of each channel of the device 5 according to the indications on the indicator of block 18. At the same time, the number of the channel being tested is displayed on the indicator of block 6. After checking all the channels of the device 5, the button 11 is pressed and the device is set, and on block 6 zeros are written to carry the devices to the socket. In the initial state, the indicators will indicate about the readiness to conduct about 40 45 50 55 Invention Formula A device for testing control devices, comprising a logic switch connected to an indicator unit, a control unit, the outputs of which are connected to the control inputs of the logic switch, and a clock generator, characterized in that, in order to expand the functionality, two pulse counters are inserted into it, bit comparison unit, additional indicator block, pulse spreader, code generator, frequency divider and synchronization block, 514429 4b6 the outputs of which are connected to the impulse inputs, the bit inputs of which counters, and inputs - with outputs connected to the outputs of the imager control unit, clock generation code, output of the bit comparison block and bit comparison block, the output through the pulse extender the inputs of which are connected to the output connected to the first input of the logical pulse counters, while the inputs of the switch, and to the second input of this additional indicator block switch via frequency divider connected to the outputs of the first counter connected to the output of the clock generator.