SU1441383A1 - Device for extracting extreme number - Google Patents

Abstract

The invention relates to computing technology and can be used ... tf f aitf PTG i.E if - used in the construction of specialized data processing tools. The purpose of the invention is to increase speed. The device contains analysis nodes 1, which include a group of elements OR 2, a group of elements SH 3, a group of elements OR 4. Binary codes of the analyzed array of numbers are received at the inputs of the analysis nodes, with the highest bits coming to the first analysis node. When input numbers are supplied in the direct code, the smallest of the input numbers is formed at the outputs of the device, and the largest of the input numbers. 1 il. ff / L with & (L 7t 4 4 OE 00 OO 7t

Description

1U41383

The invention relates to automation and computing and may

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single, i.e. on numbers that are known to be larger than the minimum given

be used in digital automatic control systems, as well as in specialized data processing devices.

The purpose of the invention is to increase the speed,

The drawing shows a diagram of the device.

The device contains analysis nodes, where m is the number of bits and analyze 1x numbers. The analysis nodes contain the group of elements OR 2, -2, where n is the number of the analyzed numbers, the group of elements EXTRACTED OR 3, -2 „, the group of elements OR 4. ,,. The device also contains IN1 AND

formation inputs 5, -5, inputs 6 - 6 permit the analysis of numbers, information outputs 7, -7, and outputs 8 - 8 of the sign of an extremal number. The device works as follows.

Binary codes of the analyzed array of numbers arrive at the inputs 5, –5 of the analysis nodes, and the highest bits arrive at node 1. When the input numbers are fed in the direct code, the smallest of the input numbers is formed at the outputs, and the largest in the inverse one. At the same time, the inputs 6 - 6 of those numbers whose analysis is allowed are given a logical zero signal, and those numbers whose analysis is prohibited is a signal of a logical one.

In the first analysis node 1, using the elements OR 2 ,, 2, ...., 2, combined at the output with the assembly AND, the formation of the output 7 (. Most significant bit of the code of the smallest number) occurs.

If at least one of the input

numbers that are not prohibited for analysis; if there is a zero in the i-th bit, then a zero will be generated at output 7; devices. At that, the elements EXCLUSIVE OR 3f of those numbers oi in the i-th category of which are zero, will form a logical nhd signal at their outputs, and the elements EXCLUSIVE OR 3 of those numbers otj, in the i-th category of which will be one, will form on their outputs exits a signal of a logical unit. This signal will go to the elements

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OR 2;; the next node is available, replace the bits of the numbers a-, -a on

In the future, the signal, the logical unit goes to the inputs of the elements OR 4; , 4. etc. Thus, a single signal at the output of the element OR 4; or the element EXCLUSIVE OR 3 prohibits further analysis of the number a.

If the i-e bits of all non-prohibited numbers for analysis are equal to one, then at output 7 a signal of a logical unit is formed, and at the output of the elements of a TRUE OR 3t. these numbers are a logical zero signal, i.e. i-M bit will not reject a single number.,

20 A logical zero is stored at that output (s) 8, corresponding to which the numbers are minimal.

Claims (1)

Invention Formula A device for extracting an extremal number containing m analysis nodes, where m is the number of bits of the analyzed numbers, each analysis node contains n OR elements, where n is the number of analyzed numbers, the i-th information input of the j-ro analysis node, where i 1 , 2, ..., p j 1,2, ..., m, is the input of the j-ro bit of the i-ro of the analyzed number of the device, the information output of the j-ro of the node of the analysis is the output of the j-ro bit of the extreme the device numbers, the output of the i-ro element OR the k-ro analysis node, where k 2,3, ..., (m-1), is connected to the i-th control input of the group (k + 1) -ro node nalysis, analyzing input resolution i-ro number of devices connected to the i-th control input node group of the first analysis of a difference ga me e ayusche By the fact that, for the purpose of speeding up, n elements - .CHOOLING OR elements are entered into each analysis node, n OR elements are entered into each kth analysis node, the first inputs of the ix OR elements and EXCLUSIVE OR j-ro analysis node are combined and connected to the i-th information input of this analysis node, the second input of the i-ro element OR is combined with the first input of the (i + n) -ro element OR k-ro analysis node and connected to the i-th control 31141383 the main input of this analysis node, the second output of the j-ro analysis node, the output The first inputs of the i-x of the elements OR of the first-ro element of the EXCLUSIVE OR (the k and t-th analysis nodes are connected to the -1) of the analysis node are connected to the third control input with the corresponding input of the i-ro and the second input (i + but of the first and t-th analysis nodes, + n) -th elements OR k-ro node, anahod resolution of analysis of i-ro number of output, output of 1 elements of ISKGYOCHA device is connected to iM of the control-Al or (t - 1) -th and the n-th node is the input of the second node of the analysis; The j-ro analysis node is combined and the sub-analysis node and the 1st output are connected to the second inputs of all elements of the extremal number of devices EXCLUSIVE OR ri informational.