SU1441328A1 - Device for checking phase sequence in three-phase mains - Google Patents

Abstract

The invention relates to phase metrics and simplifies the device. The device contains indication elements 3 and 4, for example LEDs, pulse shapers 5 and 6, and resistors 10-12. The introduction of the elements BANE 1 and 2, the phase-shifting voltage divider 9 and the formation of new functional connections allows for a decrease in the phase shift of sinusoidal voltages up to the values of one order with the time of operation of logic elements to significantly reduce the selection of one of the compared signal sequences, if the drivers of 5 and 6 pulses are made in the form of diodes, 2 cells.

Description

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The invention relates to phase metering and can be used for; control of the sign of the phase difference of two rhinusoidal voltages in a three-phase network.

The purpose of the invention is to simplify the device,

Fig, 1 shows a diagram of the device; FIG. 2 shows diagrams of the operation of the device.

The device contains the elements of the prohibition 1 and 2, the output of the element of the prohibition 1 is connected to the prohibiting input of the element prohibiting 2, the output of the element prohibiting 2 is connected to the prohibiting input of the prohibiting element. The outputs of the elements BANKS 1 and 2 are connected, respectively, the elements of the ZIL display (for example, LEDs), the second inputs of the elements BANKS 1 and 2 through the formers 5 and

6 pulses are connected to the outputs, respectively, of the 7 and 8 phase-converting voltage dividers 9, which include series-connected resistors 10, 11 and 12. The inputs 13 and 14 of the device are connected respectively

with the second terminals of the resistors 12 and 10, and the outputs 7 and 8 of the divider 9 are connected to the terminals of the resistor 11, the resistor 12 may be absent.

The device works as follows.

Compared sinusoidal voltages, for example phase A and B, are supplied to the inputs 13 and 14 for a three-phase network. Here, the phase shift between the voltages at the inputs 13 and 14 is, as shown in the diagram of FIG. 2, 120 degrees, with respect to the body or the neutral conductor. The resistance of the resistor 11 is chosen approximately three orders of magnitude lower than the resistances of the resistors 10 and 12, therefore the phase shift between the voltages acting relative to the housing at the outputs

7 and 8 is a divider 9, is a fraction of a degree, and the shift between the indicated voltages is in time (at the frequency

50 Hz) - less than one microsecond. From sinusoidal voltages, the formers of 5 and 6 pulses form a sequence of pulses, the duration of which is close to the duration of the half period of the sinusoidal voltage on the voltage. If the pulse at the output of the imaging unit 5 is ahead, then entering the input of the prohibition element 1, it passes to its output and, entering the prohibiting input of the prohibition element 2, prevents the output from the output of the prohibitory 2 from passing to the output of the imaging device 6 until the impulse at the imaging output 5, Thus, on the display element 3, for half the period of the sinusoidal voltage, a voltage is applied to the log, using the latter as the LED, it emits light, which is perceived by the operator as constant th glow. At the exit of the BANCH element. 2, at the end of the pulse, the output of the BANCH I element can occur with a pulse of substantially less than a microsecond, but this cannot cause the LED 4 to glow.

The shift of the mezkida by sinusoidal voltages with a duration of 1 µs is conditional. Since the response time of modern logic elements is tens and nanoseconds, the indicated shift time can be significantly reduced, if necessary.

If a pulse is output at the output of the imaging unit 6, then the LED 4 is luminous.

Thus, by minimizing the phase shift of sinusoidal voltages to values of one order of time with the response time of logic elements using divider 9, it becomes much easier to select one of the compared signal sequences (pulsed, rectangular, or in the form of half-sine, if drivers 5 and 6 are made in diodes), and the number of elements in the device is reduced, which simplifies the device for controlling phase rotation in a three-phase network,

Invention formula

A device for controlling phase rotation in a three-phase network, containing two pulse shapers and two display elements, characterized in that, in order to simplify the device, two BASE elements and a phase-shifting voltage divider, two inputs of which are connected to the input terminals of the device, are introduced

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first and second output .., the first element of the indication of the voltage divider is connected to the output terminal through the corresponding prohibiting input of the second element

BAN, to the output of the second element BAN - the second element of the display and

Respectively, the first and second pulse shapers are connected to the inputs of the first and second BAN elements, to the output of the first BAN elements.

prohibiting the entry of the first element of the ban.

Bx, i3 dxi

Exit 7 EXIT eight

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BAN, to the output of the second element BAN - the second element of the display

prohibiting the entry of the first element of the ban.

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Claims (1)

Claim A device for controlling phase rotation in a three-phase network, containing two pulse shapers and two indication elements, characterized in that, in order to simplify the device, two elements are PROHIBITED and a phase-shifting voltage divider, two inputs of which are connected to the input terminals of the device, the first and second outputs Phase-isolating voltage divider through respectively the first and second pulse shapers connected to the inputs of the first and second elements FORBID, to the output of the first element FORBID connected the first element t indications and prohibiting the input of the second element is PROHIBITED, to the output of the second element is PROHIBITED - the second element of the indication and prohibiting the entrance of the first element is PROHIBITED. Out -f * J L. Out 2 ------— ¹ ---------- 1 - Fig. 2