SU1437843A1 - A.c. voltage stabilizer - Google Patents

Abstract

The invention relates to secondary power sources. The purpose of the invention is to increase the efficiency of the stabilizer while maintaining high accuracy in stabilizing the output voltage. The goal is achieved in that the power amplifier 1 is connected between the input and output pins, and a second reversing counter 7, a reset node 15, a code combining node 8 multiplying the digital-to-analog converter 9, a voltage divider 10, the first and second keys are entered to control it. 12 and 13, an inverting amplifier 11. Moreover, the first output of the mapatopa 5 is connected to the sprouting input of the first 6 and the summing input of the second 7 reversible counters, the second output of the cocharator 5 is connected to the sum 1-1 of the first roar rsivnyh counters, the first and second comparator outputs are also connected with the first and second buses startup control unit 14. The outputs of the first and second reversible meters are connected to the first and second inputs of the code combining unit 8, as well as to the first and second information inputs of the control unit 14. The voltage at the output of power amplifier 1 is inphase or antiphase with the voltage at the output of source 2 of alternating voltage and varies depending on the voltage to be stabilized and the voltage at the output of source 2, 3 nl. feJ --- 0 and oh O) IHkUlTUI

Description

The invention relates to electrical engineering and electrical measuring equipment. It can be used in sources of secondary electrical power supply of electronic devices, in highly stable reference or adjustable alternating voltage sources, as well as for regulating and stabilizing the output voltage in constant voltage converters. variable.

The purpose of the invention is to increase the efficiency of the stabilizer while maintaining the high accuracy of the stabilization of the output voltage. i FIG. 1 shows a functional diagram of the stabilizer in FIG. 2; a functional diagram of the control unit in FIG. 3 is a diagram of a code combining node.

The alternating voltage stabilizer contains a power amplifier 1 whose output is connected in series with the output of the alternating voltage source 2, an output voltage measurement node 3 connected to the stabilizer output, a reference voltage source 4, comparator 5, first and second reversing counters 6 and 7, node 8 of the combination of codes 5 multiplying the DAC 9, voltage divider 10, connected by an input to the output of an alternating voltage source 2, an inverting amplifier 11, the first and second keys 12 and 13, control unit 14 and node 15 reset. The comparator 5 is connected by the first input to the output of the node 3 measuring the output voltage, the second input to the input of the source 4 of the reference voltage. The output of the comparator 5 is connected by the subtracting input of the first and summing input of the second reversible counters B and 7, the second output of the cockshare 5 is connected to the summing input of the first and the subtractive input of the second reversing counters 6 and 7o

codes are connected respectively to the outputs of the first and second reversible counters 6 and 7. The output of the code combining unit 8 is connected to the digital input of the multiplying DAC 9, connecting the output a little to the control input cr of the power amplifier 1. The voltage divider 10 is connected by an output to the inputs of the first and second keys 12 and 13. The output of the first key 12 is through inverti 0

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The dummy amplifier 11 and the output of the second key 13 are directly connected to the analog input of the multiplying CAC 9. The control unit 14 is connected by the first and second information inputs to the outputs of the first and second reversing counters 6 and 7, the first and second trigger buses with the first and second outputs of the comparator 5, the first and second outputs with counting inputs, respectively, of the first and second reversible counters 6 and 7, the first and second switching outputs with control inputs of the first and second keys 12 and 13. The reset node 15 is connected to the output with we reset the first and second up-down counter 7 and b.

The control unit 14 (FIG. 2) contains a pulse generator 16, the first is the fourth element AND 17-20, the first and second elements are NOT-NE 21 and 22, the first and second differentiating elements 23, and 24, the first and second triggers 25 and 26.

Code combining unit 8 can be executed on two-input RTOi elements, the number of which must be taken equal to the number of multiples of the DAC 9. The first inputs of the OR elements form the first input, the second inputs form the second input, and the outputs output the node of the code combining 8.

The device works as follows.

The output voltage of the stabilizer is equal to the sum of the voltage Unffr, taken from the output of the alternating voltage source 2, and the voltage of the additive and about, taken from the output of the power amplifier 1.

The amplitudes of the output voltage of the stabilizer Ugj ,, are converted by the measurement unit 3 to a constant voltage, the magnitude of which is proportional to Ugji. The comparator 5 compares the voltage at the output of the measurement unit 3 with the constant voltage U of the source 4 of the reference voltage.

When the stabilizer is turned on, the reset node 15 with a short pulse sets the first and second reversible counters 6 and 7 to zero 1sh. At the outputs of the first and second elements, IS-NE 21 and 22 appears 1, which through the first and second differentiating elements 23

and 24 resets the first and second triggers 25 and 26.

If the amplitude of the output voltage of the stabilizer is less than the set one, then level 1 from the first output of the comparator 5 will go to the summing input of the second reversible counter 7 and to the input of the second trigger 26. The output of the second trigger 26 is set to 1, opening the second key 13 and allowing the pulses to pass from generator 16 and mylcov through the second element I 18 to the counting input of the second counter 7. The state of the second counter 7 will change and the binary code from its output through the node 8 of the code combination will be fed to the digital input of the multiplier 9. The analog input of multiplying DAC 9 through the second key 13 will receive non-inverted voltage from divider 10. The amplitude of the alternating voltage at the output of the multiplying DAC is proportional to the product of the amplitude of the alternating voltage by its analog input by the binary number supplied to its digital input . The alternating voltage from the output of the multiplying DAC 9 is fed to the input of the power amplifier 1, which creates an additional voltage in phase with the voltage of the stabilized source 2. As a result, the amplitude of the output voltage of the stabilizer will increase until it is equal to the specified one.

The state of the first reversible counter 6 will remain unchanged, since O at the outputs of the first trigger 25 and the second circuit IS-NOT 22 prohibits the passage of pulses from the generator output 16 pulses through the element 17 to the counting input of the first reversible counter 6. The first key 12 will be closed on its control input.

Suppose that when the stabilizer is turned on, at the output of the power amplifier 1 some additional voltage is established, in-phase with the output voltage of source 2. When the voltage of source 2 suddenly increases, level 1 from the second output of comparator 5 goes to the summing input of the first reversible counter 6, to the subtracting the input of the second reversible counter 7 and the input of the first trigger 25. At the output of the first trigger 25

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in Wits 1, preparing the third element AND 19 to form the turn on signal of the first key 12 and the first reversible counter 6. However, they are turned on if there is also a second element IS-HE 22 at the output, i.e. when the switch is on. reversible counter 7 to the zero state. Since the second reversible counter 7 is fed to the subtracting input 1, the second output of the comparator 5 is fed 1, and the outputs of the second trigger 26 and the first element 5 21 allow the pulses from the output of the generator 1 bm to the counter input of the second reversible counter 7, the state of the counter varies so that the binary number at its output decreases. This leads to a decrease in the amplitude of the voltage at the output of the multiplying DAC 9 and, consequently, to a decrease in the additional voltage at the output of the power amplifier 1. As soon as the second reversible counter 7 is set to the zero state, the level 1 from the output of the second element IS-NOT 22 resets the second trigger 26. At the output of the fourth element And 20, an O inhibit receipt of pulses to the counting input of the second reversing counter 7 and the switch 1 is formed. 1st second key 13. At the same time, occurrence 1 at the output of the second element IS-NOT 22 generates a turn-on signal of the first key 12 and allows the arrival of pulses from the generator output 16 pulses to the counting input of the first reversing counter 6, to the summing OD 1 which is supplied from the second output of the comparator 5. The logical number of the output of the first down counter 6 starts to increase. 5 Accordingly, the voltage, antiphase voltage of source 2, at the output of multiplying DAC 9 and at the output of power amplifier 1, increases. To the analog input of multiplying DAC 9, a voltage that is antiphase to source 2 is supplied from the output of inverting amplifier 11. As a result, the output voltage of the stabilizer will decrease until it is equal to the specified one.

In this device, the accuracy of stabilization of the output voltage of the stabilizer is determined by the number of bits of the multiplying DCT 9 and the accuracy 0

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The stabilization of the output voltage of the source 4 of the reference voltage.

Along with a high accuracy of stabilizing the amipud of the output voltage, the high speed of the automatic stabilization circuit is also provided,

With a pulse frequency of 16 pulses, many

higher frequency stabilized AC voltage, the speed of the stabilizer is completely determined by the speed of the node 3 changes in the output voltage. ,

The device is economic, since if the output voltage of the stabilized source 2 corresponds to the specified voltage of the additive at the output of the power amplifier 1 is zero and the power consumed by the stabilizer becomes minimal. In addition, the output of the stabilizer power amplifier is connected in series with the output of a variable voltage source. This allows maximum use of the output power of the alternating voltage source.

The control unit and two reversible counters eliminate sudden changes in the amplitude and phase of the additive voltage.

Claims (1)

Invention Formula An alternating voltage stabilizer - NIL, containing a power amplifier connected between the current and output terminals, an output voltage measuring unit connected to the output The output of the coagrator is connected to the summing input of the first and subtractive input of the second reversible counter, the first and second output of the comparator are also connected to the first and second control unit start buses, the outputs of the first and second reversible meters are connected to the first and second inputs of the code combining unit, and also with the first and second informatdion inputs of the control unit, the output of the reset unit is connected to the reset buses of the first and second reversible meters, the counting inputs of which are connected to the first and second outputs of the unit control, the output of the code combination unit is connected to a digital input of a multiplying digital-analog converter, the output of a voltage divider connected by inputs to the input terminals is connected to the inputs of the first and second keys, the output of the second key is connected, and the output of the first key is connected via an inverting amplifier with an analog input of a multiplying digital-to-analog converter connected by an output to a control input of a power amplifier, the control inputs of the first and second keys are connected to the first and second ereklyuchayuschimi output control unit, said control unit is arranged on the alternator and mylcov, coupled output to the first input of the first and second AND gates, whose second inputs are connected to outputs sootvetstvenno- third and fourth AND gates, the first and second elements the outputs, the reference voltage source, 40 AND-NOT, connected by outputs to the percomparator, connected by the first input to the output of the measuring unit, the second input to the output of the reference voltage source, the first reversible counter, the control unit, which differs 45 second triggers, the outputs of which u with the fact that, in order to increase the efficiency of the stabilizer while maintaining high accuracy of output voltage stabilization, a second reversible counter, a reset node, a code combining node multiplying the D / A converter, a voltage divider, the first and second keys that inverts the amplifier, the first output of the comparator is connected to the subtractive input of the first and summing input of the second reversible counter, the second input of the fourth and third elements, respectively, as well as through the first and second differentiating elements, with the first and connected to the second input of the third and fourth And elements, respectively; the outputs of the first and second And elements are the first and second outputs of the control unit; the outputs of the third and fourth And elements are the first and second switching outputs of the control area; the inputs of the first and second elements are NOT the first and the second information inputs of the control unit, and the inputs of the first and second triggers, the first and second control unit start buses. FIG. Z.