SU1432543A1 - Data transfer arrangement with star-shaped topology - Google Patents

Abstract

The invention relates to a data transmission technique and is intended for use in local computing networks with random access of subscriber stations to broadcast media. The purpose of the invention is to increase productivity by eliminating conflict situations when transmitting data. The data transmission device contains a central bus 4 and P mates, each of which contains a receiving amplifier 5, a trigger 6, a delay element 7, an And 8 element. elements OR 9, and 10, element 12, delay element 13, transmitting amplifier 14, amplifiers 15 and elements of the IPI 16. Subscriber sg

Description

cl

four; from th

WITH

Phi1.1

Sky stations are connected to mate 1 blocks. Subscriber stations work with the following protocol. In the event that the data point of the data layout for transmission, the subscriber station: 1) checks for the presence of a transmission on bus 4; 2) if there is no transmission on bus 4, then it starts transmitting the packet; 3) in the case of collisions of packets on bus 4, it stops transmitting the packet and proceeds to the first point (the packet transmission continues to the highest priority station). 2 hp f-ly, 3 ill., 2 tab.

The invention relates to a data transmission technique, in particular, is intended for use in Local Area Networks with random, concurrent access of subscriber stations to a wide range of data transmission media.

The purpose of the invention is to increase productivity by eliminating conflict situations during data transfer; FIG. 1 is a block diagram of an i data device with a star-shaped topology; in fig. 2 - I is the block diagram of the subscriber station in FIG. 3 is an embodiment of the implementation of block I mapping.

A: The device contains P conjugation blocks 1, data receiving line 2 from: subscriber station, transmission line 3

data to the subscriber station, the central: 4 ishlna, receiving amplifier 5, I trigger 6, delay element 7, AND element 8, elements OR 9 and 10, trigger 11: element 11, element 12, element 13 for - 1 holder, transmitting amplifier 14, P amplifiers 15, (P-2) of elements OR 16 J Subscriber stations and the re-arrangement scheme of such a station are not shown. A subscriber station, for example, may contain a memory block 17 to which; connected transmitting 18 and receiving 19 amplifiers (Fig. 2).

The interface block (Fig. 3) contains a receive 20 and a transmitting 21 amplifiers, elements OR 22 and 23, triggers 24 and 25, elements And 26 and 27.

To facilitate understanding of the features of the proposed data transmission device, the following explanations are necessary.

In local area networks with random, competitive access of subscriber stations to the broadcaster

In the data transmission medium, each subscriber station is accessed in accordance with the established protocol. In particular, for the subscriber station the following protocol variant is possible. At a random moment of the appearance of a data packet for transmission, the subscriber station: 1) places the packet in its buffer memory unit; 2) checks for transmission on line 3; 3) if the transmission in line 3 is absent: it starts the transmission of the data packet; 4) when transmission occurs in line 3, it stops transmitting its data packet and proceeds to step 2, otherwise sends the packet to the end, and then clears the buffer memory and proceeds to wait for a new packet to appear.

The data packet transmitted to the subscriber station contains a preamble in the form of a sequence of signals 1 and O (for example, 101010 ...) and an information part. The repetition period of signals 1 and 0. In the preamble is determined from the condition that the duration of action 1 is equal to the duration of P, and the duration of 1 is greater than or equal to the propagation time of this signal through block 1 and bus 4, i.e. from the receiving amplifier 5 of one block 1 to the transmitting amplifier 14 in another block 1 of the conjugation.

The duration of the preamble. the data packet is chosen to be larger than the maximum signal propagation time between two subscriber stations through the transmission device

data with a star topology. Between retransmissions of data packets, a pause is established, needed to determine if the data is terminated15

eleven

 ABOUT

neither the previous and the beginning of the subsequent packages; the pause duration is longer than the propagation time of signals through the receiving amplifier of the subscriber station.

An information packet of data follows immediately after the preamble and contains the addresses of the transmitting station, the recipient station and the necessary data.

At the moment the data packet preamble arrives from the subscriber station via reception line 2, each conjugation block 1 may have the Free, Busy or Neutral condition depending on the state of its triggers 6 and 11. The unit 1 is installed in the specified state by the data packet preamble coming for from the data receiving line 2, or from the bus and from the output of the IZH 16 element. Each block 1 interfaces the following protocol:

1. All blocks 1 provide connection-25 if trigger 6 of line 2 with bus 4 is in busy state or bus 4 with line 3 in free, neutral state.

2. Each block 1 can go from the Zan state to the Svoden state or vice versa when the sigils of packets are used only from bus 4 or only from line 2, respectively.

3. Block 1, installed in the Zanned state, provides for a transparent transmission of the packet over Shi-35 to 4 and installation of all the remaining blocks 1 into the Free state.

4. With simultaneous installation, any other (k-1) -th block is sucked.

Corresponding to signal 1 preamp amplifier triggers 6 and 1 given in t

20

thirty

In each block of the packet with the amplifier 5 to 6 and through the first input

trigger 11 - to confirm the input of the trigger OR 9 and the R input of trigger 6 (if there is no D input from bus 4, the trigger is later than 1 on the delay is turned on and through the circuit pack element dan and the amplifier input these signals

70 YANI ZAN T In several blocks 1, the right to broadcast is received by block 1, the closest in sequence number to the first block 1,.

Consider the work of the proposed data transmission device (figure 1) with the given preliminary explanations.

If the trigger is 6 in O, and the trigger is 11 in 1, the packet 1 preamble signal acts on the D-input of trigger 6, and through delay 7 and the IDN element 9 on the C input of trigger 6. However, since signal 1 from the output of the trigger 11, then the installation of the trigger 6 in 1 at the C input is blocked and it remains in the state O. At the same time, the signal 1 of the preamble operates through the element Suppose that from the data receiving line 2 to the input of the receiving amplifier k-ro. .....

Block 1 of the conjugation receives the preamble ment OR 10 at the C input of trigger 11 and, in the form of a sequence 101010 .... In this case, the following situations are possible: all the remaining device blocks 1 are in the Free or Neutral state, one of the match blocks. 1 is in the Busy state, the (k-th) -th block, simultaneously with k unit is in the Zan t state set to 55

depending on the state 1 or O (there is a preamble signal 1 from bus 4 or not) of the D input of trigger 11, it confirms state 1 or I sets it to state O. When 11 is set to O, the trigger will

blowing signal 1 of the preamble of the packet from reception line 2, acting on the D input

Any other block, for example, a (k-1) -th block.

Accordingly, after the arrival of the preamble signal 1 from the output of the receiving amplifier 5, the states of the flip-flops 6 and 11 (on the direct output) are possible. one.

Table 1

15

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 ABOUT

5 if trigger 6

five

0

0

0

five

In each block 1, the signal 1 of the preamble of the packet from the reception line 2 goes through the amplifier 5 to the D input of the trigger 6 and through the delay elements 7 to the first inputs of the elements 8, ..., 10.

In state 1, and the trigger 11 is in O, then these states are confirmed by the C input of trigger 6 from the output of the OR element 9 and the R input of trigger 11 to the output of trigger 6 (if the signal 1 from the bus 4 absent, arrives at the D-input of the trigger 11 at the same time or later than 1 through the D-input of the trigger 6 on the delay element 7). Block 1 remains switched on in the Zan state, and through element 8 transmits packet signals to the input of element 16 and the input of amplifier 15, from the output of which these signals go to bus 4.

If the trigger is 6 in O, and the trigger is 11 in 1, the packet 1 preamble signal acts on the D-input of trigger 6, and through delay 7 and the IDN element 9 on the C input of trigger 6. However, since signal 1 from the output of the trigger 11, then the installation of the trigger 6 in 1 on the C input is blocked and it remains in the state O. At the same time, the signal 1 of the preamble acts through the ale. .....

ment OR 10 at the C input of the trigger 11 and, ment OR 10 at the C input of the trigger 11 and,

depending on the state 1 or O (there is a preamble signal 1 from bus 4 or not) of the D input of trigger 11, it confirms state 1 or I sets it to state O. When 11 is set to O, the trigger will

cop OR 10 at the C input of the trigger 11 and

blowing signal 1 of the preamble of the packet from reception line 2, acting on the D input

514

the trigger 6 and through elements 7 and 9, via the C input of the trigger 6 sets it to state 1, and the signal from the single output of the trigger 6 is confirmed, the setting of the 11 C trigger on its R input.

Thus, the conjugation block 1 is turned on in the state: Zan t (trigger 6 is in 1, trigger i11 is in O), with the result that AND 8 is unlocked, and I I 12 is blocked. From the output of the element And 8. the signals of the packet arrive at the input I of the amplifier 15, and from its output on the shiI well A.

I In the case of a block state, the Neutral junction is turned on to the I I state immediately, with the first j signal 1 of the preamble, and in the case of the I state of the block 1 it is free to turn it into the Leave state. after pre-switching to the Neutral state, i the delay value of element 7 is chosen j or greater than the propagation time of the signal through the element OR 9 and the trigger 6. In this case, I ensures that the trigger 6 is reliably mounted and the possibility of the effects of defective signals at the output of the element And 8. nstallation block state Its 1: Boden implemented as follows. The signal 1 packet from the bus 4 is valid; on the D input of the trigger 11, through the OR element 9 - on the S input of the trigger 6 and on elements 13 and 10 on the C input of: the trigger 11. As a result, the trigger 6 I is set to the state O or; condition on condition that at its D-input the signal of 1 packet from line 2 was missing or came within the time resolution of trigger 6 with respect to the signal at the C-input of trigger 6. Trigger 1

set to state 1, block element OR 9 for further effects. In this case, delay element 13 is chosen identical with element 7 and performs the same functions. After installation in block 1, the state of the element And 8 is blocked, and the element 12 is unlocked and signals from bus 4 arrive at its input and from its output through amplifier 14 pass to line 3.

It is assumed that the delay of the elements OR 9, the trigger 6, the elements 8

3

10 and 12; trigger 11, element 16 are small compared with the duration of the signal 1 (O) of the preamble of the packet. This position corresponds to the case of using elements of high-speed logic (ECL) to implement the fastest data transmission device. For this reason, to maintain the required level of reliability, it is necessary to introduce additional delay elements 7 and 13, as well as the implementation of the symmetric setup scheme for the states of block 1 Zan t, Free on D-BHOD and C-inputs of the flip-flops 6 and 11.

When packets arrive simultaneously on lines 2 from several blocks 1, the signals 1 of their preamble set these blocks to the Zan t state (trigger 6 in 1, trigger 11 in O). The signals from the outputs of the elements And B in all the blocks in the Zan t state are fed to the inputs of the corresponding amplifiers 15 and from their output to the bus 4. At the same time, the signals from the outputs of the elements And 8 and k-ro block 1, where, 2, ..., (P-1), are fed to the input of the element OR 16 and from its output to the R input of the trigger 6, to the S input of the trigger 11 and to the second input of the element OR 16 (k + 1) -ro block 1.

The signal is transmitted successively through a series of elements OR 16 corresponding to (P-k) blocks 1, to the R input of the trigger 6 and to the S input of the trigger 11 of each of these blocks 1. As a result, all the (P-k) blocks 1 will be forced to

Free trigger 6 in O, trigger 11 - in 1. Thus.

0 0

the state of blocks 1 is set up independently of their previous state, with only one 45 of the interfaces 1 receiving the right to broadcast the packet.

When using the variant of the interface block depicted in Fig. 3, the principle of operation is similar to that described above.

Accordingly, after the arrival of the signal 1 of the preamble from the output of the receiving amplifier 20 to the D input of the trigger 24 and C input of the trigger 25, the states of the triggers 24 and 25 (on a single output) shown in Table 2 are possible.

ten

This signal is outputted from trigger output 24 to the R input. If the duration of the signal 1 of the preamble of a packet is longer than its propagation time through element 26 I, bus 4, element OR 23, trigger 25, then there is always a reliable preservation of the status of Zan t of the k-ro interface 1 In the first situation, if the kth inter - 15 packet signal on bus 4 from its own subscriber station.

the face is in the Zan state, the preamble signal 1 through the OR element 22 and directly on the C input confirms the trigger 24 in the state 1, and the triggered subscriber station.

The signal from the output element OR 16 k-ro interface is fed to the R input

ger 25 in O. Confirmation of the state of 20 setting zero trigger 24 and through

the OR element 23 on the S input of trigger 2 (k + 1) -ro of interface 1. As a result, the triggers 24 and 25 (k + 1) -ro of interface 1 are forcibly set 25 (confirmed) in the corresponding states O and 1, that fixes the Free state (k + 1) -ro of the interface 1 (if, then). The signal from the output of the OR element 16 (k-l) of the flip-flops occurs at the time of the change from O to 1 of the front) signal 1 of the preamble. Since trigger 24 was already in state 1

the OR element 23 to the S input of the trigger 25 (k + 1) -ro of interface 1. As a result, the triggers 24 and 25 (k + 1) -ro of interface 1 are forcibly set 25 (confirmed) in the corresponding states O and 1, that fixes the Free state (k + 1) -ro of interface 1 (if, then). The signal from the output of the element OR 16 (k-l) r

then simultaneously

with confirmation of the condition of the triggers 24 and 25, the packet signals pass through the elements AND 26 to the bus 4 and to the input of the element 16 OR, respectively.

. The signal 1 of the preamble of the packet passed through the AND element 26 of the k-ro block 1 30 of the interface is absent, since on the bus 4, the element acts on the input, this interface is in the AND 17 of all interfaces 1 and through the element OR 23 no S - input of setup 1 of trigger 25. Since in the first case interfaces 1, except for k-ro, are in the Neutral or Idle state, the signal 1 s

35

SRI Free and maintained in this state by signals from bus 4 as

and all interfaces 1, except k-ro. .

If in this situation the k-th interface is in the Neutral state, then the trigger 24 is set to 1 via the C-22 element at the C input, and the trigger 25 is set to O, i.e. The k-th interface 40 is set to the Zan-t state. When the trigger is set to 24, 1 signal of the preamble of the packet from the output of the amplifier 20 of the k-ro interface 1 {comes first to the D-input of the trigger

bus 4 sets or confirms state 1 of flip-flop 25 respectively, and state O of flip-flop 24 remains unchanged. As a result, the signal 1 of the preamble of the packet and, subsequently, the entire sequence of the signal of the packet passes through if in this situation the k-th interface is in the Neutral state, then the trigger 24 through the SHSh 22 element at the C input is set to 1, and the trigger 25 - in Oh, i.e. The k-th interface 40 is set to the Zan-t state. When the trigger is set to 24, 1 signal of the preamble of the packet from the output of the amplifier 20 of the k-ro interface 1 {comes first to the D-input of the trigger

due to 1 D input

blocked (1 at zero output 45 24 and through the delay of the element OR 22 - flip-flop 24) element AND 27 and transmitting amplifier 21 to the transmission line of all other interfaces 1, except k-ro. In the kM interface1, set to the Zante state, the 50 1 signal in the bus 4 always acts on the S input of the trigger 25 later or simultaneously with the action on the R input of the trigger 25 of the signal from the single output of trigger 24. As a result of 55 of these signals on The outputs of the trigger 25 appear signals 1. However, the D-input of the trigger 24 and the other input of the element OR 22 used to work

to the C input of the trigger 24. The delay introduced by the OR element 22 is sufficient for a reliable installation of the trigger 24 to 1 by the action of the trigger signal 24 during this delay. The magnitude of the delay of the element OR 22 is limited only by the minimum value of the resolution of the trigger 24 in time and its selection is not critical. The state O of the trigger 25 is confirmed by its C-input, and after installing the trigger 24 into 1 signal from its 14325438

preamble signal 1. Therefore, the thrung ger 24 remains in state 1. After the termination of the signal 1 of the preamble of the packet on bus 4, the trigger 24 remains

 G, and the trigger 25 - in

hold 10

 15

This signal is outputted from trigger output 24 to the R input. If the duration of the signal 1 of the preamble of a packet is longer than its propagation time through element 26 I, bus 4 element OR 23, trigger 25, then the condition of Zan k of the signal 1 of the packet signal on bus 4 from its own subscriber station is always maintained.

The signal from the output element OR 16 k-ro interface is fed to the R input

setting zero trigger 24 and through

the OR element 23 to the S-input of the trigger 25 (k + 1) -ro of interface 1. As a result, the triggers 24 and 25 (k + 1) -ro of interface 1 are forcibly set (confirmed) in the corresponding states O and 1, which fixes Free state (k + 1) -ro of interface 1 (if, then). The signal from the output of the element OR 16 (k-l) ro

interface is missing because this interface is in

interface is missing because this interface is in

SRI Free and maintained in this state by signals from bus 4 as

and all interfaces 1, except k-ro. .

If in this situation the k-th interface is in the Neutral state, then the trigger 24 is set to 1 via the C-22 element at the C input, and the trigger 25 is set to O, i.e. The k-th interface 1 is set to the Zan-t state. When the trigger is set to 24, 1 signal of the preamble of the packet from the output of the amplifier 20 k-ro interface 1 first arrives at the D-input of the trigger

4 and through the delay element OR 22 -

due to 1 D input

24 and through the delay element OR 22 -

to the C input of the trigger 24. The delay introduced by the OR element 22 is sufficient for a reliable installation of the trigger 24 to 1 by the action of the trigger signal 24 during this delay. The magnitude of the delay of the element OR 22 is limited only by the minimum value of the resolution of the trigger 24 in time and its selection is not critical. The state O of the trigger 25 is confirmed by its C input, and after the trigger 24 is set to 1 by the signal from its single output, the trigger 25 is kept liing the state O by the R input of the installation in O.

If in the first situation, the 1c-th interface is in the Free state, to signal 1 from the output of the amplifier 20, the Trigger 25 is set to O, since its D input has a constant logical-Q ifo signal, and the trigger 24 remains in O, because at the moment of transferring from O to 1 the signal of the preamble of the packet, one input of the element OR H2 was already on the other input, the signal D P - from the trigger trigger 25 Set trigger to 24 to 1 The effect of the next packet preamble signal i tl.

I Thus, in the first situation, if the k-th interface 1 was in the | Neutral state, then it is set

p state n

Zan t, and if he was in

c | os free, then set to the zan state, with a delay of one period of the transmission frequency of the preamble fgnal signal, i.e. with the m | daily installation, the Neutral state. Otherwise, the work of only 5 || devices in the first situation occurs in all cases as well as for the c) beam, when the kth interface is in the Zanta state.

I; In the second situation, when one of the 1 interface is in the state, for example (), the device is working as follows. The Preamble signal, having set the Zan state to the kM interface 1, passes through the AND 26 element to the bus 4 and to the input of the AND 27 and OR 23 elements. Through the element: YLI 23 the trigger 25 (kt) -ro of the interface 1 is set to l and the signal IV from its single output through the element OR 22 at the C input of the trigger 24 | sets the latter to O. As a result, (k-1) -th interface 1 is set to: Freeze to idle and 27 unlocked and passes the packet signals from the bus 4, through the amplifier; tel 21, to line 3; for the rest, the operation of the unit (city does not differ from its operation in the first situation.

In the third situation at the same time

arriving on receive lines 2, for example k-ro and (k-l) -ro of interfaces 1, the packet preamble signals 1 simultaneously set these interfaces Q d

0

25

0

gg, 0 45 9

gg

These signals are transmitted to bus 4 and pass on line 3 of the transmission of only interfaces 1 set to the idle state. Simultaneously, the signals from the element ID 26 and (kl) -ro of interface 1 are transmitted via the OR element 16 to the R input of the trigger 24, through the OR element 23 to the S input of the trigger 25 of the k-ro interface 1 and to the second input of the IL element 16 corresponding to the k-th interface 1. The signals from the output of the AND 26 element of the k-ro interface 1 are transmitted through the OR element 16 to the R input of the trigger 24, through the OR element 23 to the S input of the trigger 25 (k + 1) -ro of the interface . As a result, the signals are transmitted sequentially through the OR 16 elements and set the forced (P-. K-1) of the interfaces 1 to the Free state, i.e. All interfaces 1, whose serial numbers are greater than (k-1) -th, transmit signals from bus 4 to the 3rd-transmission line.

Claims (3)

1. A data transmission device with a star topology, containing P interface blocks, the first information inputs of all interface blocks are interconnected, which differs from the fact that, in order to increase productivity by eliminating collisions in data transmission , the P-2 elements of the IL are additionally introduced into it, the first output of the k-ro interface block (k 1, ..., P) is connected to the first information inputs of all interface blocks, the first output of the first interface block is connected to first input of the first element OR the lock input of the second interface block, the output of the b-th element OR is connected to the first input of the (L + 1) -th element OR and the lock input of the (L + 2) -th pair of the interface, where, ..., (P-3 ), the output (P-2) of the element-: OR is connected to the blocking input of the P-th interface block, the first output of the a-th block of the interface is connected to the second input of (a-1) -th element OR, where, ..., (P-1), the second information input of the k-ro interface block is the kM information input of the device, the second output of the k-ro interface block is the kth information output of the device. . 2. The device according to claim 1, about tl and - in that the interface block contains two delay elements, two OR elements, two AND elements, two triggers, a receiving and transmitting amplifiers, the first information input of the block is connected to the information the input of the first trigger, the first input of the first OR element and the first delay element — with the first inputs of the second OR element and the first element AND; the output of the first element AND is connected via a transmitting amplifier to the second output of the block, the output of the second element AND is connected to the first output of the block, second info The formatting input of the block is connected to the information input of the second trigger, the blocking input of the block is connected to the installation inputs of the first trigger and the second trigger reset, the information input of the second trigger is connected via the second delay element to the second inputs of the first and second elements OR and the first input of the second element I, direct the output of the first trigger is connected to the third input of the first OR element, the output of which is connected to the synchronization input of the second trigger; the output of the second OR element is connected to the synchronization input ne of the first trigger, the direct output of the second trigger is connected to the second input of the second element AND and the reset input of the first trigger Hera, the inverse output of the second trigger R 0 g 5 0 th block zero. ra is connected to the second input of the first element I. 3. The device according to claim 1, about tl and - in that the interface block contains two elements OR, two elements AND, two triggers, receiving and transmitting amplifiers, the first information input of the block is connected to the first inputs of the first ILH element and the first element I, the output of which is connected via the transmitting amplifier with the second output of the unit, the second information input is connected through the receiving amplifier with the first input of the second element I, the information input of the first trigger, the first input of the second element OR, and the input of the strobe of the second trigger, input b the blocking unit is connected to the reset input of the first trigger and the second input of the first OR element, the output of which is connected to the installation input of the second trigger, the direct output of which is connected to the second input of the second OR element; the output of which is connected to the gate entrance of the first trigger, the direct output of which is connected to the second input of the second element I and the reset input of the second trigger, the inverse output of the first trigger connected to the second input of the first element I, the output of the second element I the second trigger is connected to the input logical1 f Fiu.2 f P