SU1418926A1 - Conference communication arrangement for delta-modulated systems - Google Patents

Abstract

The invention relates to telecommunications. The purpose of the invention is to increase the noise immunity of a conference. The device contains a block in which 1 level signal is applied, a channel selection block 2, a combining and switching unit 3 delta-modulated (DM) signal-. The synchronization block and block 4. The device analyzes the DM sequences of the speech signals of the conference subscribers (A), forms their estimated levels, and on this basis determines the activity of each of them. In this case, the signals of only active A or A are combined with the highest value of the estimated signal level, which excludes the influence of the pause sequences of silent A signals on the total speech signals. The device determines the situation when only one of A is active, and commutes its DM signal directly to the inputs to the other participants in the conference. This eliminates the noise and distortion created when combining. The goal is achieved by eliminating the influence of the pause sequences of the DM signals of silent A on the total conference signals, and if only one of the A is active, by switching its DM signal on the inputs to the other participants. A device according to claim 2 f-li from-. characterized by the implementation of block 2 channel selection. Given il. Fulfillment - all device units. 1 hp f-ly, 5 pcs. (L

Description

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The invention relates to telecommunications and can be used for organizing telephone conferencing in digital communication systems using delta-modulation (DM) for analog-to-digital conversion of voice signals of subscribers,

The purpose of the invention is to increase the noise immunity of the conference

Fig. 1 shows a functional electrical circuit of a conference device for N participants of a digital communication system with DM; in section 2 - the functional diagram of the channel selection block is functional; FIG. 3 is a functional block diagram of a level signal extraction unit; FIG. 4 is a functional diagram of a unit for combining and switching DM signals; FIG. 3 shows a functional block diagram.

The conference device for the DM system comprises a block 1 for level signal allocation, a block for channel selection 2, a block 3 for combining and switching DM signals, and a block 4 for synchronization.

The channel selection block contains a shaper 5 threshold level, element NOT 6, the first additional element AND 7, the second additional element AND 8, the first and second input registers 9 and 10, the first comparator 11 digital signals, the switch 12 digital signals, the first and second And 3 and 14 elements, first and second output registers 15 and 16, second and third comparators 17 and 18 digital signals, third and fourth elements And 19 and 20, first and second D-flip-flops 2 and 22, first and second comm. - tators 23 and 24 analog signals, first and second comparators 25 and 26 Byh signals.

The block for selecting the level signals contains a multiplexer 27, a register block 28, an element STI-NOT 29, an element 30, a block 31 registers, an element OR-32, a second block 33 of the shift registers, an element AND W-NOT 34, the elements 35 and 36, element OR 37, block 38 of registers, element RSHI 9, counter 40, decoder 41, ND-flip-flops 42, N integrators 43,

The unit for combining and switching signals contains multiplexers 44 and 45, decoders 46 and 47, elements OR 48, delta modulators 49 and 50, adder 51, delta modulator 52, multiplexers 53.

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The unit synchronization unit contains frequency dividers 54 and 55, timer 56, element And 57, counter 58, decoder 59, trigger 60, D-flip-flop 61, elements And 62 and 63.

The device conferencing systems for DM works as follows.

In the conference device, the level signal extractor 1 generates estimated signal levels of subscribers. Consider the operation of this unit in accordance with its functional scheme; my (fig.Z).

Input DM-signals from N conference subscribers are sent to the information:; ionic inputs of the N-channel multi; 27, which converts N Laraleral input digital channels into one output. At the same time, the transfer rate of the output digital channel is N times the speed of the input channels, t, e. for one period of the DM signal, the output of the multiplexer 27 KONT is read one symbol of the DM signal; the first of each of the N subscribers, Dn of this K-bit binary counter 40, where K log 2 N, forms the N channels of subscribers in digital binary code on the basis of the signal fj fp, where f-nf is the clocking frequency, and by means of the K outputs controls their switching in the circuit. The frequency of the signal f g is N times higher than the frequency of DM-. subscriber signals. These frequencies are modeled in synchronization unit 4, the functional diagram of which is shown in FIG. 5. In this block, frequency divider 54 divides the frequency of the clock pulse signal in such a way: fm Nfj, and frequency divider 55 divides f by N. Sequence-1a processing of subscriber signals in block 1 of the level signal extraction allows an increase of N times speed, almost N times to reduce the amount of equipment, compared with the scheme of parallel analysis on the activity of DM subscribers subscribers.

At the V-code N-channel multiplexer 27, we obtain a digital DM-sequence of subscriber signals compacted in time, which arrives at the information input of a block of 28 registers consisting of N 4-H-FIND shift registers. The number of bits of the shift registers of this block is determined by the peculiarity of the com

31

pandirov when DM DM analog voice signals of subscribers. A DM with a syllable companding of the pitch is considered, changing the quantization step in the following subsections of four homogeneous premises, for which even 4-bit shift registers are used, i.e. in our case. The number of registers in block 28 is determined the number of time channels (subscribers), so that the characters of the DM-signals of each of the N subscribers are recorded in their 4-bit shift register. Thus, in four bits of the first shift register of block 28, we obtain a sequence of four DM-signal characters subscriber on the four bits of the second shift register-sequence of four symbols of the DM signal of the second subscriber, etc., Connecting the 4-bit shift registers to the inputs and outputs of the block 28 registers, as well as in blocks 31, 39 and 38 of the register , a switching signal of the time channels in the circuit arriving at the K control inputs of the register block from the K-bits of the binary counter 40 is carried out. Information is recorded in the registers on the clock edge of the frequency signal fg received at the clock inputs from the blocks register at.

When subscribers are active in their DM signals, bundles of four or more homogeneous packages appear. They are extracted by OR-NOT 29 elements (bursts of zeros) and an AND 30 element (bursts of units) and converted into bursts of units, with the length of bursts of DM signals shortened by three characters. Further, the time-bundled packets of DM-signals of active subscribers arrive at the inputs of the And 35 (packs of units) and 36 (sets of zeros inverted into units) and, accordingly, the info. Operational inputs of blocks 33 and 31 of the registers. The blocks 33 and 31 of the registers, together with the elements OR-HE 32 and 34, as well as the elements 35 and 36 serve to eliminate the interfering effects of alternating packets of zeros and units characteristic of companded DM, if there are high-frequency interfering signals in the analog part of the subscriber path. impacts, even relatively low. Block 31 of registers together with the element OR NOT 32 is

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It includes the perception of an AND 35 batch of units, which appears on the next eight clock cycles of the DM signal, immediately after the batch of zeros, and accordingly a block of 33 registers with the OR element does NOT eliminate the perception by the And 36 element of a batch of zeros inverted into a batch of units of

Volume 0 and 30, which appears for the next eight cycles after a stack of units. Three-unit-shortened streams of units and subscriber signals that are compacted in time DM5 inverted into I and O are combined by the OR element 37 and fed to the information input of the register block 38 and one of the inputs of the OR element 39, Block 38 of the registron together with the element

0 OR 39 restores the duration of packs of DM signals, Thus, at the output of the element OR 39, we get im-. the pulse sequence of packs of DM-signals ak.

5 active subscribers, which contains information about the current values of signal levels of participants in the conference. connection. The absence of packs in the time channel of the silent subscriber is

The zero value of its signal level is 0, the sequence of packets of DM-signals of active subscribers in compressed time channels is fed to the information D-inputs of ND-flip-flops 40. D-flip-flops 40 are joint. locally with the decoder 41, under the control of the switching signal of the time channels coming from the outputs of the K-bits of the binary counter 40, the digital sequence is multiplied

0

the compacted in time N channels subscribers. At the same time, the duration of the symbols is increased by a factor of N

 O and G

digital signals packs

in the subscriber channels, their initial duration at the input is considered by considering the mogo-block. The integrators 43, when the digital sequences of bundles of DM-signals of active subscribers arrive from the outputs of D-flip-flops, form signals of the estimated levels of conference subscribers. The value of the estimated subscriber signal level depends on the length of the packs of the selected homogeneous symbols and the frequency of their appearance in the subscriber channel. The constant time of integrators should be commensurate.

with the duration of the syllable of speech and is 2-5 ms. Thus, the level signal extracting unit 1 generates estimated signal levels of the subscribers participating in the conference.

Channel 2 block selection node control block 4 synchronization by means of input gate register gating signals, output registers gating, channel selection, channel selection, signal selection control, level compares the values of estimated levels with each other, as well as on the basis of comparison with the help of the DM-signal selection signals DMSJ of the first channel A, the selection of the DM signal of the second channel B, the disconnection of channel B controls the switching in block 3 of the input DM signals of the subscribers to the devices for converting and combining the EU and the number of active subscribers M: 2, then block 2, by means of the selection signals of the DM signal of channel A and the selection of the DM signal of channel B, controls the connection of the DM signals of two subscribers with the highest current values of the speech signal level to the inputs ( Channels A and B) of a two-channel DM-Signa-unification device. block 3. At the same time, from the information outputs of block 3, all subscribers, except subscribers of channels A and B, receive DM-signal, corresponding to the sum of speech signals of active subscribers A and B, and DM-signal from the subscriber arrives at the output of subscriber A B and vice versa. In a situation when only one subscriber is active (A), the channel B signal is active at the corresponding input of block 3. In this case, the output of the other subscriber A directly arrives at the output AHC of subscriber A, while this subscriber receives a pause DM-sequence. - the strength of the silent subscriber of channel B

In the channel selection block 2, the first and second input registers 9 and 10, the first and second switches 23 and 24, and switches 12, the comparators 25 and 11, and the element NOT 6, the first and second additional elements And 7 and 8 are the choice of two subscribers with the highest estimated levels of speech signals. The scheme works as follows. The inputs To the control signals of block 2 alternately receive signals of subscriber numbers i from O to, N -1 in the parallel binary code. Correspondingly, the level signals (cyPi) of subscribers alternately arrive at the first input of the first comparator 25 via the first switch 23. At the channel 2 input of the channel 2, the signal initially acts with a logic level of O. At the same time, through the switch 12, it is controlled by the switch 12. the inputs of the first switch 23 are in effect the signal of subscriber number J, in the following: 1 in the first input register 9; the inverse input of the second comparator 26 receives the signal level of the J-th subscriber. Thus, the second comparator 26 compares the current i-ro subscriber level signal with the subscriber level signal, the number of which J is recorded in the first input register 9. Upon arrival at the inputs K of the control signals of the next number i, the strobe signal 2 is fed to the strobe them-. ; ., pulse. When CyPi CyPJ is satisfied by this pulse, the new input number i is written to the first input register 9 through the first additional element 7. Thus, at the end of the polling of all N subscribers, the subscriber number with the highest current RMS value will be recorded in the input register 9, then the signal at the channel select input will be transferred to one state and the subscriber polling will be repeated, PS its end in the second input register 10 recorded the number of the second most active subscriber. The digital first comparator 1 1 eliminates the possibility of the ability to write the same subscriber number in the first and second input registers 9 and 10.

The subscriber polling operation is completed by sending a pulse to output output registers with which the numbers of the most active subscribers can be rewritten from the first and second input registers 9 and 10 to the first and second output registers 15 and 16, respectively, as a result of which the A and B blocks will be presented to these subscribers 3, Such a census is allowed provided that channels A and Bg are free, i.e., subscribers to whom these channels have previously been provided are in an inactive state (their current values of SUs are less than some threshold smooth activity - P), active subscriber channels A and B assayed circuit comprising the second

714

the comparator 26, the shaper 5 threshold level - P, the second and third digital comparators 17 and 18, the first and second triggers 21 and 22 and the third and fourth elements And 19 and 20.

The scheme works as follows. When, when a subscriber polling operation is performed, the current subscriber number i coincides with the subscriber number of channel A (B) recorded in the first (second) input register 15 (J6), a signal appears at the output of the second (third) comparator 17 (18). This signal permits the passage of the next pulse of the alignment of the input registers to the clock input of the first (second) trigger 21 (22). At the same time, a CYPi is fed to the reverse input of the second comparator 26. If SUR P, i.e. If subscriber i is inactive, then the output of this comparator will act on a logical 1 signal, which will be written into the first (second) trigger 21 (22) with the next gating pulse of the input registers. Thus, at the end of the subscriber polling procedure, a single signal at the output of the first (second) trigger 21 (22) corresponds to the release of channel A (B) and through the first (second) element And 13 (14) allows recording the new subscriber number in the first (second) input register 15 (16).

In the event that the subscriber of channel B is inactive, the rest of the subscribers of the total speech signal of subscribers A and B do not make sense, and for direct transmission to subscribers of the DM signal of subscriber A, the signal C from the output of the second trigger 22 is fed to block 3,

A variant of the functional circuit of the unit 3 combining and switching DM signals (Fig. 4) provides for analog combining of the signals of two active subscribers. For this, the DM signals that are selected by the signals Select the first channel and Select the second channel, the output of the multiplexers 44 and 45 are fed to the inputs of the delta demodulators 49 and 50. The demodulated speech signals are summed in the analog adder 51 and the resulting sum signal is modulated into the delta modulator of torus 52. Decoders 46 and 47, multiplexers 53, and the OR 4F elements constitute the circuit for switching signals to

926

conference participants, who control the screens, select the first channel, select the second channel, and deactivate the second channel.

Figure 5 presents a variant of the functional block synchronization. In this scheme, the clock signals f and DM are formed sequentially

0 enabled frequency dividers 54 and 55. The control signals for selecting the RMS during the polling operation of subscribers are formed at the outputs of the counter 58 with a conversion factor K N + li Signal

5, the channel selection is removed from the output of the counting trigger 60, which is clocked by the transfer signal of the counter 58. In turn, the counter is clocked by the frequency pulses fp ,. In this way

0 the duration of the survey

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comrade is 2-. Period for-

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start this procedure, which must correspond to the syllable interval

5 speeches (4-10) ms, set by timer 56. At the end of the polling procedure, which is indicated by a single signal at the output of the D-flip-flop 61, copied from the output of the decoder 59, is disabled

0, further outputting the strobe pulses of the input registers of block 2, and a gating pulse of the output registers is output. With this pulse, timer 56 is set to the initial state g. A zero signal from the output of timer 36 prohibits the subsequent clocking of the counter and the issuance of gating pulses until the specified ratio is reached. recalculation timer 56, which

0 thus defines the time interval between successive subscriber polling procedures. When a single signal appears at the output of timer 56, the polling procedure starts again from the initial state of the counter 58 and the zero state of the trigger 60.

In this way, the conferencing device performs a DM-sequence analysis.

Q in the sequence of speech signals of conference subscribers, the formation of their estimated levels and, on this basis, the determination of the activity of each of them. In this case, the device combines the signals of only active subscribers or subscribers with the highest: the desire for the magnitude of the estimated level of speech signals, thereby eliminating the influence of pause sequences

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c: igialop MOiriainnx аРо} {Oiton on suprana sigma gpl conference conferences, which is understood: the noise immunity of the latter (signal-to-noise ratio). Lonly active, the device detects the situation when only one subscriber is active, and commutes its DM signal directly to the inputs to the other participants in the conference, thereby eliminating the noise and distortions created by the combination.

Claims (2)

1. The conference unit for systems with delta modulation, which contains the combining and switching unit of the delta-mbdulironannyh (DM) signals and the synchronization unit, the first tact-Bbrfi output of which is connected to the clock input of the blog; The signals, the number of informational inputs and outputs of the unit for combining and switching the DM signals and the clock input of the synchronization unit are respectively the N inputs and outputs of the information signals and the input of clock pulses of the conferencing device for systems with delta modulation her about aphids that, in order to improve noise immunity,; a level signal extractor and a channel selection block N information inputs of a level signal extractor are connected, respectively, to the N information inputs of the DM signal combining and switching unit, the clock input of the level signal extractor block is connected to the second clock output of the synchronization block N outputs of the extractor level signal the level signals are connected respectively to the N inputs of the level signals of the channel selection unit, the first and second outputs of the gating signals, the output of the channel selection signal and K outputs with the control unit of the synchronization unit are connected respectively to the first and second inputs of the gating signals, the input of the channel selection signal and the inputs of the control signal of the channel selection unit, whereby the outputs of the first channel selection signal, K outputs of the second channel selection signal and the output of the second channel disconnect signal sample channel connected respectively to the inputs 892610 signal selection channel nepnoj-o, K 1;: by the second signal paths of the second channel selection: a and by the input si | -dala of disconnection of the second channel of the combining and switching unit / M signal. 2. The device according to claim 1, about tl and - h Ayushees that the block channel selection contains the first and second Q analog signal switches, first and second analog signal comparators, threshold level driver, NOT element, first and second input registers, first and second 5 output registers, first, second and third comparators of digital signals, first, second, third and fourth elements And, first and second additional elements And, a switch diffraction 0 out of 1 signals, the first and second D-triggers, while the N information inputs of the first analog signal switch are connected to the N information inputs of the second switch; The 5 geo signals are the N information: they are the inputs of the channel selector unit, the L-switch of the first analog signal switch is connected to the direct input of the first comparator analog signals. 0 n, 1 and the inverse input of the second analog signal analog signal generator, the output of the second analog signal comparator is connected to the inverse input of the first analog signal comparator, the threshold level input of the former is connected to the forward input of the second analog signal comparator, the output of the first analog signal comparator connected to the first inputs Q c fvogo and second additional This input And, the output of the second analog signal comparator is connected to the D input of the first and second D-trigger - pciB, K of the control inputs of the first .g switch analog signals, connect; neny respectively with K information1-: on the inputs of the first and second input registers, To the first inputs of the first, second and third kompara5 tsra digital signals and are To the input and control signal of the channel selection unit, the second input of the first additional element I is connected to the second input of the second additional element I and the first inputs of the third and fourth elements I and is the first input of the gating signal of the channel selection unit, the third input of the second additional 1 11 A element I is connected to the control input of the digital signal switch, to the input of the element is NOT and is the input of the channel select signal of the channel selection block, and the output of the element is NOT connected to the third input of the first additional AND element whose output is connected to the gate input of the first input register The second additional element And is connected to the input of the strobe signal of the second input register, the outputs K of the bits of which are connected respectively to the inputs of the second channel of the digital signal switch with To information inputs of the second output register, outputs To the bits of the first input register connected to the information inputs of the first output register, with To the inputs of the first channel of the digital signal switch, To the second inputs of the first comparator 1SHFW signals, the output of the inequality signal of which is connected to the fourth input of the second an additional element And the second input of the first element And is connected to the second input of the second element And and is the second input of the gating signal of the channel selection block, the outputs K times rows switch digital signals -. connected to K control inputs 612 the second switch analog signals, the output of the first element And is connected to the input of the strobe signal of the first output register, the output of the second element And is connected to the input of the strobe signal of the second output register, the outputs of which bits are connected respectively to K the second inputs of the third digital signal comparator and are the outputs of the signal of the second channel of the channel selection unit, the outputs K of the bits of the first output register are connected to K second The inputs of the second digital signal comparator are the outputs of the first channel selection signal of the channel selection block, the equal signal output of the second digital signal comparator is connected to the second input of the third And element, the output signal of the third digital signal comparator is connected to the second input of the fourth And element which exit it is connected to the clock input of the second D-flip-flop, the output of the third element I is connected to the clock input of the first D-flip-flop, the output of which is connected to the first input of the first element This And, the output of the second D-flip-flop is connected to the first input of the second element And, and is the output of the disconnect signal of the second channel of the channel selection block. ftrj | w / v1. lns2cltoi CItfl f VV l foHtpn ftgrfifc {y Latet Clt tmp one . I dm l d. z ri aLffel Omn 6 6tiSeiH c evtoptMce Tdgt "-J 13 fiu.b ZZ; s