SU1415380A1 - D.c. to multiplle-step quasi-sine voltage converter - Google Patents

Abstract

The invention relates to electrical engineering, more specifically to converters of direct voltage to alternating voltage with a quasi-sinusoidal or stepwise sinusoidal form of output voltage. The goal is to increase the reliability of the converter, i.e. eliminate the possibility of malfunctions and emergency situations in the converter operation at f abrupt change in voltage 1 at the converter output. For this purpose, a software signal generation unit 1, having a software sinusoid code output, a clock output, a zero signal output, a polarity control output, an analog-to-digital converter 2, a code comparison unit 3 having a code input, a number priority output, is entered into the converter the first input, the output priority of the number at the second input, two matching circuits 4 and 5, M cell control units 7-9. When the output voltage deviates from a program value, a clock pulse is received at the corresponding input (summing or subtracting) of the reversing counter 6 and the output voltage changes discretely until the error is eliminated. 9 ill., 1 tab. (L ate 00 00 F1 / Y / Vtta

Description

The invention relates to electrical engineering, in particular, converters of direct voltage to alternating with quasi-sinusoidal or step-sinusoidal form, and can be used in installations of guaranteed power supply of consumers of alternating current, systems of autonomous power supply, high-precision electric drive.

The purpose of the invention is to improve the reliability of operation of a constant voltage to quasi-sinusoidal converter,

FIG. 1 shows a functional diagram of the converter with three power cells; in fig. 2 - functional block diagram of the formation of software signals; in fig. 3 and A, power cell control units / in FIG. 5-6 are functional diagrams of power cells; in FIG. 7 - power unit of the converter, consisting of three power cells; in fig. 8 is a key switching table; FIG. 9 - time diagrams of the keys.

The converter (Fig. 1) includes a block 1 of generating program signals, an analog-digital converter 2, block 3 of code comparison, two two-input circuits 4 and 5 coincidence, a reversible counter 6, blocks 7–9 of cell control, power converter cells 10 -12, and also a source of 13 direct current

The program signal generating unit 1 has a software sinusoid code output, a clock output, a zero signal output, an polar control output, an analog-to-digital converter 2 input is connected to the output of the converter, a code comparison unit 3 is connected to the output of the analog-digital converter 2 by the first code input , the second code input is connected to the output of the software sinusoid code of block 1, the output of the priority number on the first input is connected to the first input

ten

15

0

five

five

0

five

0

(K) are connected to the corresponding bits of the code output of the reversible counter 6, and the outputs, the number of which is equal to the number of keys in the power cells 10-12, are connected to the control inputs of the corresponding keys of the power cells 10-12, the output of the clock pulses of unit 1 is connected to the second the inputs of circuits 4 and 5 coincidence; the output of the zero signal of unit 1 is connected to the reverse input (R) of the reversing counter 6, the power cells 10-12 by the power inputs are connected to the direct current source 13, and their power outputs are connected in series photoelectret in general.

The Converter operates as follows.

At the output of the software sinusoid code of block 1 (Fig. 1), a code X is formed, the value of which at each instant of time is proportional to the instantaneous value of the software of the stepwise approximated sinusoid. Code X is continuously fed to the second input of block 3 of code comparison to the first input of which continuously comes from the output of ADC 2 code y, the value of which at each time instant is proportional to the instantaneous voltage value at the output of the converter.

Codes X and y are continuously compared in block 3 of the code comparison. If those. the voltage at the output of the converter is less than the program value, then from the priority output of the number at the second input of block 3 of code comparison, the enabling signal (xy, in Fig. 1) is fed to the first input of the second circuit 5 of coincidence, and the clock pulses from the output of clock pulses of the block 1 begin to arrive at the summing input of the reversing counter 6. In the reversing counter 6, the summing of clock pulses begins, the code value at the output of the reversing counter 6 increases, in blocks 7–9 of the control cells forming

For the first coincidence circuit 4, the output of which is turned on and off by the gray circuit is connected to the subtracting input of the reversible counter 6, the number priority output at the second input is connected to the first input of the second coincidence circuit 5, the output of which is 1and dc; 1 is connected to the summing input 55 of the reversing counter 6, blocks 7-9 of the cell management of the first inputs (P) Paul :. Yu4. Iy to control output polar gyo block 1 second inputs

the corresponding keys of the power cells 10–12, the voltage at the output of the converter increases in proportion to the increasing code at the output of the reversible counter h until it reaches the prog 1) amm value, i.e. until it becomes xy.

If in some time (1 - (OMLMIT time, the voltage is n .. :: -: olg 1p (mfrazato; 1

The switching on and off circuits of the corresponding keys of the power cells 10-12, the voltage at the output of the converter increases in proportion to the increasing code at the output of the reversible counter h until it reaches the prog 1) amm value, i.e. until it becomes xy.

If in some time (1 - (OMLMIT time, the voltage is n .. :: -: olg 1p (mfrazato; 1

more software value, i.e. for X, then the enable signal from the output of the priority number at the first input of block 3 of the code comparison arrives at the first run of the first circuit 4, the clock pulses from the output of block 1 begin to flow to the subtracting input of the reversible counter 6, the code decreases at the output of the reversible counter 6 and in proportion to its voltage at the output of the converter, until it is.

Thus, the output voltage is constantly catching up with the program value. In this case, the tasks of forming the required form of the output voltage and stabilizing its magnitude (effective value) are performed.

To eliminate any unforeseen processes in operation, at the end of each period of a software sinusoid from the output of a zero signal of block 1, the signal of a zero value of a software sinusoid arrives at the obnuyushchy input (R) of the reversible counter 6 and sets it to the 0-0 state.

FIG. 2 shows a functional diagram of the block 1 of generating program signals. The software signal generation unit 1 includes a master oscillator 14, the output of which is the clock pulse output and is connected via frequency divider 15 to the counting input of counter 16, whose code output is connected to the address input of the programmable memory 17 (ROM), and ROM 17 has at least M + 1 bits of the output code, where M is the number of power cells of the converter and the number of bits of the control code at the output of the reversible counter 6.

Block 1 works as follows

In the initial state, the counter 16 is reset. From the output of the master oscillator 14, clock pulses with a frequency fjr are output to the clock pulse output of block 1 and to the input of the frequency divider 15, from the output of which clock pulses with frequency f о F- / kg, where kg is the division factor, are sent to the counting input of the counter 16 .

The first M bits of the output code of the ROM 17 form the output of the program sinusoid code. In these bits, a code is written corresponding to a software step-approximated

sine wave The bit (M + 1) -and output code of the ROM 17 forms the polarity control output. This section contains the control code for the polarity of the output voltage — power cells.

The overflow output (+ P) of counter 16 forms an output zero signal.

The volume of the counter 16 S 2, where N is the number of bits of the output code of the counter 16, must be equal to or not exceed the number of addresses of the ROM 17.

The table shows the address numbers of the ROM 17 and the values of the code values written to these addresses, provided that the ROM 17 is selected as the ROM volume, which satisfies the considered circuit with three power cells (M 3).

20

25

11th; 1x table

РЗ

A variant of the cell control unit (Fig. 3) is shown for the case when the power cell is made according to the scheme of a single-phase bridge inverter on transistors with reverse diodes and a transformer output. The block consists of two, two-input elements AND 18-19, element OR 20 and one element NOT 1, has two inputs K and P and four outputs on which logical functions are realized: F k-p; Fj k-p

P. 4 P The variant of the cell control unit (Fig. 4) is given on the day of the case when the power cell is made according to the circuit with the primary winding of the transformer. The block has two inputs K and P and three outputs on which the logical functions F, k-p are implemented; F; k-p; Fj (k .p) (k-p) k.

The above block example consists of the element HE 22, two two-input

0

B

0

five

five

0

elements And 23-24, two-input element AND-NOT 25.

The power cell (Fig. 5) is fully on the bridge circuit and includes an output transformer 26, reverse diodes 27-30, transistor switches 31-34.

The control functions of the transistor switches: for the transistor switch 31 F k.p, for the transistor switch 32 F2 К -Р, for the transistor switch 33 F Р, for the transistor switch 34 F.J p.

The power cell with the device for shunting the primary winding of the transformer (Fig. 6) includes an output transformer 35 with a midpoint in the primary winding, two transistor Q switches 36-37 that form the output voltage, a transistor switch 38 diodes 39-42, forming element 43 shunting the transformer primary winding. Key management functions: transistor switch 36 F k р p, transistor switch 37 F k-p, transistor switch 38 of the primary winding element 43 of the transformer F k.

The power part of the converter (Fig. 7) consists of three power cells connected in parallel along the input (along the power supply circuit) and in series - along the output circuit. The power section of the conversion includes power switches 44-55, with keys 44-47 being included in the first power cell, keys 48-51 - in the second, keys 52-55 - in the third, output transformers 56-58, and the transformer 56 enters the first cell, transformer 57- into the second, transformer 58 - into the third reverse diodes 59-70, with diodes 59-62 entering the first cell, diodes 63-66 - into the second, diodes 67-70 - into the third.

FIG. 8 shows a key switching table 44-55, and FIG. 9 are timing diagrams explaining the operation of the converter (Fig. 7) and the principle of forming the output voltage.

The technical and economic efficiency of the proposed invention is to increase the reliability of the converter's fulfillment of its main function - to provide consumers with alternating current of required electric power and quality.

The present invention makes it possible to increase the reliability of operation of the converter, the reliability of providing alternating current with electric power of a given quality of consumers connected to the output of the converter. And the requirement of uninterrupted power supply is one of the main requirements in the electric drive in autonomous power supply systems of responsible consumers.

Claims (1)

Invention Formula A constant-voltage constant-voltage quasi-sinusoidal converter containing m parallel-connected power transformer cells, each of which is a single-phase inverter with a transformer output, reversible counter as a control code generator, characterized in that, in order to increase reliability , a program signal generating unit was inserted, having an output of a program code 5mn1:; r about sinusoidal voltage, an output of clock pulses, an output of a signal corresponding to the end half-cycle of sinusoidal voltage, polarity control signal output, analog-to-digital converter, input connected to converter output, code comparison unit, first input connected to analog-digital converter output, second input to program output of software sinusoidal voltage program forming unit signals, the output priority of the number at the first input of the code comparison unit is connected to the first input of the first coincidence unit, the output of which is connected to the reversing subtraction input the counter, the output of the priority number at the second input of the code comparison unit is connected to the first input of the second matching unit, the output of which is connected to the summing input of the reversible counter, the second inputs of the matching units are connected to the output of the clock signals of the program signal generation unit, m control units of power transformer cells, first the inputs of which are connected to the output of the polar control signal of the program generating unit of the program signals, the second inputs to five 0 five the corresponding code outputs of the reversible counter, the outputs whose number is equal to the number of keys in the power transformer cell, are connected to the control inputs of the corresponding keys, the signal output corresponding to the end of the sinusoidal voltage period of the program signal generation unit is connected to the reverse terminal of the reverse counter, the formation unit software signals made in the form of a master oscillator, the output of which is the output of the clock pulses of the block and through the frequency divider connected to The input of the counter of the program signal shaping unit, whose code output is connected to the address input of a programmable memory device having at least m + 1 bit of code code, and m values forming the output of the program code of the program signal waveform, are written the program code corresponding to the instantaneous values of the stepwise approximated sinusoidal voltage, and in (t + 1) -th level forming the output  the program signal generating unit, the polarity of the output voltage of the power transformer cells is recorded; the output: repetition of the counter of the program form block of the program signals forms the output of the signal corresponding to the end of the sinusoidal voltage period of the program signal generating unit, with shunting of the primary windings or as a single-phase bridge inverter on fully controllable keys with reverse dyads, control units have 5 There are two inputs and three outputs, the signals of which are formed in accordance with the following logic functions: F, k.p, F k-p, 0 Fj (k-p) (k-p) k, where p is the signal at the output of the polar control signal of the program signal generating unit; 5 k - signal on the corresponding output of the reversible counter, with the first outputs of the control units connected to the control inputs of the keys forming the half-wave of one the polarities of the output voltage, the second to the control inputs of the keys forming the half-wave of the other polarity, the third to the control inputs of the shunting units of the primary windings of transformers, or two IHDs and four outputs, the signals of which are formed in accordance with the following logic functions , FI k.p; F, k p; F, Pi F4 P, where p is the signal at the output of the polar control signal of the program signal forming unit; I k - signal at the corresponding output of the reversible counter. the first and second outputs of each control unit are connected to the control inputs of the keys of the anode group, and the third and fourth outputs are connected to the control inputs of the keys of the cathode group. Management t-l rnos / drink No exit TaftmoSbfe impuls & / to ufK-p ig. four +  PuB. five } 23 517S3 W ll 12 a H fl IS 17 IS IS fO 21 i2 23 2 25 26 27 g 23 JO four 0000 r 1 t f / goooooooooooooooooooo ts oooooo oooooooooooo} ///// i oo oo oo o IS ooooooooo000000011 / t i g ii ti t /// / 7 (fftittftttiffiooooooeeeeooooff "/ as f t 0 9 t I lootioaoooooooocoooooo i ooeoodooooooeooooitooiiiootioe se 00000000000 c 0001 I I) 1 t f g t t 1 I i i t ft // r f I t f t f f 000000000000000 92 0 I 0 1 0 I 0 1 0 1 0 1 0 I 0 0 0 0 0 0 0 0.0 0 0 0 0 S3 ooooooeouoooooaoiototototoiote s 000000000000000} Jltltllilffttt five t f f f I f {1 I J t 1 f / JOBOOOOOOOOOOOOO 9ui.a -f Rig. 6 ag.7 Fig s