SU1411766A1 - Switching network - Google Patents

Abstract

The invention can be used to build matrix multi-machine computational systems with and. . allows organizing the simultaneous transfer of arrays of information between several pairs of computing blocks in a network with an arbitrary configuration due to the storage of network configuration information in the memory of computing blocks. To this end, the cells of the switching network are connected through their information inputs and outputs in accordance with the network topology. Computing units (digital computers) are connected to the cells of the switching network. Their memory contains information about the network topology. Using the configuration backbone, each computing unit can determine the state of the switching network and set up the communication channel it needs (the computing unit). 1 hp f-ly, 13 ill. one

Description

O) O)

The invention relates to computing and can be used to build computing systems.

The purpose of the invention is the expansion of functional capabilities due to the organization of an arbitrary network configuration.

Fig, 1 shows a functional diagram of the switching network; FIG. 2 is a functional diagram for the combination of several digital computers in a fflogo matrix computing system; in fig. 3 is a functional block diagram of the analysis of the state of the highway; in fig. 4 is a functional state sensor circuit; in fig. 5 is a timing diagram of the operation of the status sensor; ya fig. 6 - structure of control words; Fig 7 is a functional circuit of the setting unit; in fig. 8 is a block diagram of the tuner; FIG. 9 is a diagram of the switch; FIG. 10 is a codogram of the contents of the memory node of the tuning unit; in fig. 11 is a functional block diagram; in fig. 12 is a functional diagram of the switching node of the backbone of the interface unit; in fig. 13 is a functional diagram of the control unit of the interface block.

Commuting cell 1 of the interconnecting network contains an interface 2, a switch 3 and a control block, which includes a configuration block 4, a trunk state analysis block 5 and a state sensor 6, four groups of machine-to-machine exchange 7, a trunk 8 of machine exchange , group of address buses 9, group of output information buses 10, group of input information buses I5 group of command buses 12, group of control buses 13, buses 14 and 15 of control word synchronization, polling bus 16, command polling bus 17, interrupt request bus 18 , bus 19 I / O request daz bus

20query trunk configuration, bus

21 answers, setup program launch bus 22, control bus group 23, setup line 24, control settings bus group 25, settings informational group {26 settings, input bus 27 and priority output bus 28, bus sensor installation bus 29, P1inu , 30 state sensor reset, iiiHfsy 31 tuning sync bus, 32 state bus

0

five

a hinge, a state sensor polling bus 33, a first control word synchronization bus 34, a tuning bus group 35, a tuning highway reset bus 36, a DVR characteristic bus 37,

The line state analysis block 5 (FIGURE 3) contains four triggers 38..41, two elements AND 42 and 43, receiver 44, transmitter 45, element NO 46 ..

A state sensor 6 (Fig. 4) contains a comparison circuit 47, two flip-flops 48 and 49, three elements And 50 ,, 52, a driver 53, a cell number switch 54, transmitters 55 and 56.

The setting unit 4 (FIG. 7) contains - a cell number switch 57, a comparison circuit 58, an address register 59, a setting register 60, a memory node 61. TI, trigger 62, And 63 and 64 elements and delay elements 65 and 66,

The commutator 3..contains p groups, where p is the number of switched liaines, 5 research institutes, ten elements of And 67 .., 76. in each (Fig.9),

Interface unit 2 (Fig.P) contains a trunk switching node 77, control node 78, current address counter 79, number counter 80

0

0

words, register 81 information and re0

gist 82 commands, outputs 83 ... 86 and input 87 of control node 78

Node 77 switching highways

c: (Fig. 12 contains two triggers 88 and 89, four elements AND 90 .. 93, element OR 94, driver 95, four transmitters 96 .. 99 and three receivers 100 o. 102.

The control unit 78 (Fig. 13 contains a comparison circuit 103, five triggers 104-108, thirteen elements AND 109-121, element 2I-OR 122, three formers 123-125 pulses. SOC, five receivers 126-130, three 131 - 133 transmitter. Switch

134 of the digital computer.

The switching cells are combined in a uniform structure (Fig 2). intended for switching information and control commands transmitted. between digital computers 135 in the process of their functioning.

The interaction of the digital computer 135 as part of a computing system can be reduced to three modes: transferring an array of information between the digital computer 135 on the initiative of a digital sensor; transfer between digital computers

135 management team; gear mas0

five

Siva of information between the digital computer 135 initiated by the digital computer receiver

In the mode of transferring an array of information between a digital computer initiated by a digital sensor, if the initiator of information transfer is a digital sensor, then the process of information transfer is carried out in five steps: the configuration program interrogates the state of switching cells 1 of the switching network; calculates the optimal transmission path of the array of information between the digital computer 135; setting up the transmission path of the information array; transferring an array; upon completion of the transfer of the array, the path of information transfer is eliminated.

The network is set up for transferring an array of information between two digital computers 135. The program is carried out via a configuration bus 24, which contains control configuration buses 25 and configuration information buses 26.

. When accessing from the side of the digital computer 135 to the highway 24, settings may arise conflict situations caused by the simultaneous access of two or more digital computers 135 to the main line 24 of the configuration, or the digital computer 135 to the main line 24 of the network while it is occupied.

All switching cells 1 and digital computers connected to them 135 are assigned corresponding priority levels, with the priority level killing from left to right, from top to bottom (figure 2) In addition, each cell 1 and digital computer 135 connected to it has its own number.

When accessing the highway 24, the configuration conflicts are solved by the block 5 of the analysis of the state of the highway (settings). All blocks 5 are interconnected by a bus 27 (priority), with bus 27 being the input of block 5 from switching cell 1 of highest priority, and area 28 - output of block 5 for switching cell 1 of lower priority. Thus, the upper-left CVM 135 (FIG. 2) has the highest priority, and the lower-right ones

Dp synchronization of requests for setting highway 24 of the setting In the upper left cell 1, a StroSinhr gate is generated, which is provided to one of the buses 31 of the group of control buses 25 of the tuning highway 24

successively in all blocks 5 (strobe driver not shown).

The request for the tuning line 24 is received via the request bus 20 to the block 5, fixed on the trigger .38 and the leading edge of the signal C.sync. rewritten to trigger 39. The trailing edge of the p. sync. in the absence of requests from the higher-priority digital computer 135 (resolving potential bus 27) and assuming that the tuning highway 24 is free (resolving potential at the receiver 44 output), through the AND 42 element the request is copied to trigger 40 and then to trigger 41

At the output of the trigger 40, a Run Prog signal is generated. tuned on bus 22 in the digital computer 135, and

trigger 41 through the transmitter 45 sets on the bus 32 SosToMagistr. settings potential corresponding to the state of zanto. After the transition of the digital computer 135 to the setup program from

The digital computer via bus 21 generates a 3-prom signal received by which trigger 40 is reset.

The computer system is configured by the digital computer program 135 and is carried out in four stages: analysis of the state of cells in the network; calculation of the optimal path for transferring information between digital computers; setting the path of information transfer; release

highway configuration.

At the first stage, the PC 135 polls the sensors 6 of the state of the switching cells 1. The sensors 6 are polled by two commands — a software output command (VP1) and a software input command (VVP).

The first command is issuing from the digital computer via block 2 to information. the control bus 26 settings of the control word

Separate bits Usl is determined (Fig 6).

Cell number 1, digital computer number 135 (bit 1-4);

A sign of the operation being performed: a status sensor is polled and 1 is a network setting (bit 5);

the sign of the trunk to which 1 is issued (in 6 bits de) - the trunk 24 settings and (in 7 bits de) - the trunk 7;

sign of resetting the tuning line (bit 8);

the sign of the starting address (bit 9);

sign of the number of words (bit 1P);

sign of digital computers; 1 - digital receiver and O - digital sensor (bit d);

mode indicator: О - information transfer and 1 - control command transmission (bit 12).

A command from the digital computer 135 over the bus group 10 to the input of the trunk switching unit 77 of the corresponding block 2 from the digital computer 135 issues the control word code US1, while in the switching node 77 the trigger 89 is set to one state, the output of which is the output code of the digital computer 135 and signals synchronization of control words US1 and US2 are connected via elements 92 and 93 and transmitters 98 and 99 to information 26 and control buses 25

Via these buses, the USL1 is fed to the input of the circuit 47 comparing the sensors 6 of the state of all the cells of 1 network

When the number of cell 1 coincides with the code in bits US1 1-4, a single potential level is established at the output of comparison circuit 47, which is transmitted to the trigger 48 by the E 50 element (with 5p in US1 transmitted in 6p - 1)

The state of the flip-flop 49 is polled on the And 51 element by the output signal of the flip-flop 48 and the synchronized signal Sync "US1". The reset of the flip-flop 48 is detected through the driver 53o.

The timing diagram of the sensor polling (trigger 49) of cell 1 is shown in FIG. five"

The output of the trigger 48 through the transmitter 55 enters into the MicroMaster, as a signal for polling the DS, and the output of the element 51 through the transmitter 56 is connected to one of the bits Inf, tuned buses, and through the node 77 of the trunks of the block 2 is received The input command, following the command for issuing the control words USL, the program YVM 135 is entered into the RAM of the digital computer 135 the contents of the register 81 of the information block 2

Similarly, the polling of all cells of the 1st network is performed.

After interrogating the state of the cells 1, the DVR-sensor 135 program calculates the optimal transmission path and the direction of transmission within the switch 3,

The configuration of each node is provided by two software output commands VSH and V2P, which from the CVM sensor 135 issue the control words Usl and Us2 settings.

The command VSH and digital computer 135 for the group of tires 10 to the input of the node 77 of the commutation of the trunks of block 2 issues the control word code US1. At the same time, the switching node 77 establishes

the trigger state 89, to the information input of which the PSG signal arrives, and the synchronization input is a unit of 6 Stim.1, the output signal of the trigger 89

The control word and sync signals / HSS and US2 (Sync US1, Sync US2) are connected via E 92 and 93 elements and transmitters 99 and 98 to information 26 and 25 control buses of Tire Bus tuning I / O. and sync signal sync. US1 go to the corresponding inputs of all blocks 4 settings. With

the coincidence of the cell number 1, installed on the switch of the 57 number, with the code of bits 1–4 USl1, through the AND 63 element, the trigger 62 is set to one (when

this fifth and sixth bits are 1),

Following the USL of the digital computer 135, the settings information bus 26 is issued US2 settings, and one of

control bus 25 settings signal Sync US2 config.

US2 (Fig. 6) contains the address of the node 61 of the memory of setting 4, which is signaled by the Sync.

nastrs is accepted in register 59,

At each address, node 61 stores a setup code that is used to switch elements of the device 3 to provide the necessary transmission direction.

In order to appropriately configure the t-ryTaTOpa 3 combo, it is necessary to select the necessary information transfer direction from the table (FIG. 10). US2 code

the setting must correspond to this direction. After receiving the address in register 59, the output of element 65 is over; the control signal is generated by which, through the delay element 66, the code from the output of the node 61 is written to the setting register 60

The outputs of the setup register 60 are connected to the corresponding control inputs of the And 67-76 elements of the switch 3. In FIGS. 9, the control inputs of the And 67 - 76 elements indicate the bit numbers of the setting register 60 (the setting code) in accordance with the codogram (Fig. 10 ).

The final command of the tuning program must be the release highway of the tuning line, for which, from the digital sensor 135, the system is issued with units in bits 6 and 8 and the number of the digital sensor 135 in bits 1-4. In the sensor 6 state on the element And 52, a Reset Mag. Signal is generated. and, via bus 36, the line condition analysis block 5 (settings), de, is reset to the initial state. The main line 24 is accessible to work with other digital computers 135 networks.

After the information transmission path has been established between the digital sensor 135 and the digital receiver 135, the digital sensor 135 program is used to prepare the blocks 2 of the digital sensor 135 and digital receiver 135 for machine-to-machine exchange.

The training program of the conjugate blocks 2 records the counters 79 and 80 of the starting address and the array size, respectively, as well as simulating the request for issuing the first word from the DVR sensor 135. Writing into each of the counters of the CVM 135 is performed by two operations of the VSH and V2P outputs.

In the first operation, the first control word US1 appears, in the second, the second control word US2 (Fig.6).

The control word US1 and its synchronization signal Sync US1 are output to the input of the trunk switching node 77 to the communities 10 and 15, respectively. In this case, the PVS element OR 94 signal at the information input of the trigger 88 establishes a single potential, which is unit to the trigger 7 US1, fixed in the trigger 88 Through elements 90 and 91, transmitters 96 and 97, and receiver 100 connect the output information buses 10 and buses 14 and 15 transfer synchronization signals to the mainline 8 machine-to-machine exchange.

When issuing the Usl, the number of the digital computer 135 is supplied to the comparison circuits 103 of the control unit 78 units of the digital computer 135. The number of the corresponding digital computer 135 is set in the second group of inputs of the comparison circuit 103. In the selected room for the exchange of digital memory 135, the numbers are compared and the output potential of the comparison circuit 103 is set to .

Signal Sync. US1 via elements AND 109-113 in the triggers 104-108 fix the values of the corresponding

, bits Usl1 (numbers of bits are shown in Fig. 13 at the inputs of the elements And 109-113)

When recording the starting address of the array in block 2, the DVR sensor 135 is set in one state, the triggers 104 and 105, the output potentials of which and the Sync signal. A set of 2, received through the receiver 128, on the element And 118 is formed

the signal PSCHTAdr, which, through the imager 124, receives into the counter 79 the current address of the starting address of the array.

When recording the number of words of the mass in the node 78 of the control of the block 2 of the DVR sensor 135, the triggers 104 and 106, whose OUTPUT potentials and the Sync signal are set, are set to one. USMO on the element

And 119, a PSCSCHC signal is generated, which, through the imager 125, receives the number of array words into the counter 80. Similarly, an entry is made in the counters of the DVR receiver 135, and the trigger 107 is additionally set to one.

After the preparation of the channels of the machine-to-machine exchange of the CMB sensor 135 one by one

From buses 13, via the trunk switching node 77, the request to the digital computer is output to the control node 78. On this signal, received through the receiver .128, on element 2I-OR 122 a Request-Ib signal is generated, which, entering the digital sensor, suspends its operation for one cycle and from the RAM cell whose address is written in the counter 79 the first word is issued

array. The information word that is output from the DVM sensor 135 is switched by the PV1P signal at the switching node 77 to the trunk 8. This word is accompanied by the D-PRMMO polling signal outputted from the digital sensor 135 via the bus 16n to the control node 78, where 5, a request signal is generated in the CEM network. This signal is transmitted through the transmitter 132 to one of the control buses of the highway 8, and the Sync. MMO% signal is simultaneously generated on the I element and transmitted through the transmitter 131 to the corresponding trunk control bus 8.

Reception of information in block 2 proiz. is led to the register 81 by the PCRGSCHO signal generated at the control module 78 of the digital receiver 135 on the element 119 from the sync signal. received via receiver 130; Simultaneously, the request signal to the DVR through the receiver 129, element 2I-OR 122 enters the DVM receiver 135 as, the Request-To-In signal causes the r / o program; J35o In this case, the Poll D-PRMO signal is sent from the last one. On the E-120 element, a VCRGM U signal is generated, which reads the contents of the information register 81 in the memory of the DVR receiver at the address specified in the counter 79. At the same time, the same signal through the E-6 element and the Leredator. 133 arrives at the corresponding trunk of highway 8 as a signal. Request for DVMd to output the next word of information from the DVR. The state of the counters 79 and 80 is changed by the falling edge of the signal. D-PRMO polling, After the last word of the information array is transmitted to the counters 80 in blocks 2 CVM signal array 135 formed end which apparatus units 2 DCM 135 is driven to its original state

In addition, the signal end of the array. enters the digital computer 135 as a request to interrupt the current program of the digital sensor 35 and transfer the digital sensor 135 to run the program: eliminate the transmission path of information between the digital sensor 135 and the digital receiver 135 "The execution of this interrupt in the digital receiver 135 should be blocked

If it is necessary to preserve the information transmission path in order to transfer the following array of information, it is necessary to block this interrupt request and in the DVR sensor 135 ,,

The program for the elimination of the information transfer path is similar to the setup program with the difference that in blocks 4, the settings of all the cells 1 of the control word Comp. A reference is made to the zero cell of the node 6 by the name of the TIB in which 1 is written in bit II (FIG. 10). Thus, in register 60 of setting, the code 0, .e, 0, t, e is recorded, all control signals from And 67 - 76 elements of switch 3 are removed, and a Reset signal is generated at the same time as discharge 11 is output.

5 is a switch, h, with which trigger flip-flop 49 of state sensor 6 is reset via bus 30. The corresponding cell 1 is reset.

Warns control command transfer,

0 provides the transfer of command control. laziness to interrupt the current program between two lyubyg-and digital computers 135,

Setting the transmission path and switching of trunk 8 between two digital computers 135

5-for the transmission of a control command is carried out similarly to the configuration and switching of a trunk for transmitting an array of information.

Issuing a control command is performed by two output operations, B

 i

The first control word USL with the units in bits 12 and 7 and the number of the receiver CMV 135 in bits 1–4 is the first one

5 the word USL2MMO contains a transition command,

The mode criterion (12p) is received by the Sync signal, US1 in the trigger 108 of the Sync Signal control node 78.

0 Compiler 2 through the receiver 127 on the element I 121, a CCRgK signal is generated, which receives the control command in the register 82 of the commands.

5 enters the DVR receiver 135. As a request to interrupt programs 1 1 "After the control command has been processed by the signal from the DVR receiver 135, the contents of register 82 are reset via bus 17

0 teams.

The elimination of the control command transmission path between the DVR receiver and the DVR sensor 135 is carried out ana. logically, the procedure that is carried out when transferring data from the digital computer 135 of the array of information.

The mode of transmission of information between the digital computer 135, initiated by the digital computer receiver 135, is consistent

performing first a visit between the control command digital computer 35, as a result of which the digital sensor 135 enters the transfer mode to the digital computer receiver 135 of the information array.

Claims (2)

Formula of Invention  I. A switching network containing T switching cells, with the Mth information input-output of the K-th switching cell (1, ... T; M 1,., E, where E is the number of information inputs-outputs in K th switching cell) is connected to the N th information input input-output of the R th switching cell in accordance with the network topology (and 1,. „., Е, Р,. ,,) with the fact that expansion of functionality due to the organization of an arbitrary network configuration, the inputs- outputs for connecting the computational blocks of all the switching cells are about the network inputs / outputs of the network, the polling inputs of the polling of all the switching cells are connected through a group of control bus settings, the inputs and outputs of setting the operation mode of all the switching cells are connected through a group of information bus settings, the output of the permission sign for the K-th the switching cell is connected to the same input (K + O th switching cell in accordance with a decrease in the priority of the switching cells, 2. Network according to claim 1, characterized in that each switching cell contains a control unit j junction block and a switch, the first to E th informational inputs-outputs of which are the same-name inputs-outputs of the switching cell, inputs- The outputs for connecting the computational units of which are connected to the same inputs / outputs of the interface unit, the input outputs of the polling of the state of which are the same inputs and outputs of the switching cell and are connected to the same inputs and outputs of the control unit, switching events of which are connected to the switch input of the same name, (Р-ь) -th information input-output of which is connected to the information input-output of the interface unit, the input-outputs of the operation mode of which are the same name as the input-outputs of the switching cell and are connected to the same input-output control unit. 2i Iljlil ji l (I (, 1 I i ii t FIG. 2 Fig Sya1 Usag mot USD / fZ MM O Moree's memory ffaetta nastoviki. Ha ojftHKu ldrvs passive (ttpu, l 99f and, e right cp / rt) Kofluvecmte words in Nassia (10Ri, 0 ° 6 IRUS / il} command. Controls (at 1 Bit 1 yCfflj 9UB.S wff.f Network settings Nn / r.shil Hetmndfu cuhxft. HCAl Catap Cond1 Wm. Tg: K W.KB w9r. Bttx.6S 8. 61 1m.b6 .Kvivapr. Clpoc network S5 3S A one, 35 Cfpoc network Ij Js W I T - 1G