SU1403209A1 - Arrangement for overspeed protection of reversible electric drive - Google Patents

Abstract

The invention relates to electrical engineering and is intended for use in direct current valve actuators used in machine tool construction. The purpose of the invention is to increase the reliability of protection by simplifying the design of the device,

Description

. „.. bllfeE.

 b hc

hfii

zLJ L.JrJ

J

with

(L

The new mode of operation, when the rotational speed of the electric motor (ED) corresponds to the set one, at the output of the comparison unit (BS) 12 has a positive signal acting on the input of the zero-body 13. At the output of the zero-body 13 there is also a positive signal delays are fed to the input of memory block 29. The memory block 29 generates at its output 49 a single signal permitting the work of the ED. If the rotational speed of the ED exceeds a predetermined frequency, the output of BS 12 produces a negative polarity signal, which through the null organ 13 and the circuit 28 converts the memory block 29 zero state prohibiting the work of ED. When switching from a high setpoint of rotational speed to low and when braking, the braking control unit 14 triggers, which via the closing contact 43 of the executive relay 42 supplies the input of BS 12 to a polkkittelny signal, preventing a negative signal from BS 12 from outputting body 13 and prohibit further operation of the drive. Upon expiration of the time required for the brake (EDD, contact 43 is opened, ensuring the further operation of the DE at the new setpoint of rotational speed. 2 3. n, files, 1 silt,

one

The invention relates to electrical engineering and is intended for use in DC electric drives used in machine tool construction.

The purpose of the invention is to increase the reliability of protection by simplifying the device.

The drawing shows a diagram of the device.

The device 1 for protection against overspeed of the rotational electric drive 2, which includes an adjustable transducer 3 with a control input 4j cmioBb M output 5 and input 6 Prohibition of operation, the rotation speed setting device 7, output connected to the control input 4 of the adjustable converter 3, and an executive motor 8 connected to the power output 5 of the adjustable converter 3, equipped with a rotational speed sensor 9, contains the first 10 and second 11 converters, the comparison unit 12, the zero-organ 13s the brake control unit 14 tim 15 and an additional source of DC. The first converter 10 has an input output 16 for connecting to the output of the frequency adjuster rotated and output 17 is connected to the first input 18 of the comparison unit 12, the second converter 11 has an input output 19 for connecting to the output of the rotational speed sensor 9 and output 20 is connected to the second input 21 of the unit 12 comparisons. The comparator unit 12 has a third input 22 for connecting to the first output 23 an additional source 15, a second output 24 connected to the common conductor 25 of the device. The output 26 of the comparator unit 12 is connected to the input 27 of the zero-body 13 The device contains a time delay circuit 28 and a memory unit 29. The first converter 10 is implemented with the polarity of the output signal, which coincides with the polarity of the first pin 23 of the additional source 15. The second converter 11 is configured with the opposite polarity of the bypass signal.

Comparison unit 12 is provided with a fourth input 30 and is provided on four resistors 31-34, each included in the comparison unit between output 26 and the corresponding input 18, 21, 22 and 30, Braking control unit 14 is connected to output 17 of the first converter 10 and made on the operational amplifier 36, vol. 37, sixth 38, seventh 39 resistors, first capacitor 40, transistor 41 and executive relay 42 with a closing contact 43. In the braking control unit 14, the input terminal 35 of this unit is connected via a fifth resistor 37 with the first entry This amplifier 36, and through series-connected sixth 38 and seventh 39 resistors - with the second input of this amplifier.

The midpoint between the sixth 38 and seventh 39 resistors is connected through the first capacitor 40 to the common conductor 25. The output of the operational amplifier is connected to the base of the transistor 41J in the collector-emitter circuit

between the output intended for connection to the EXTRA EXT.

The main source 15j and the common conductor 25 are connected to the winding of the executive relay 42. The first output of the closing contact 43 of the executive relay 42 is connected to an input for connecting an additional source 15 to the first output 23, and the second output of this contact is connected to the fourth input 30 of the comparator 12.

The zero-organ output 44 is connected to the input 45 of the time delay circuit 28 by the output 46 connected to the first input 47 of the memory unit 29, the second input 48 of which is connected to an output for connecting an additional source 15 to the first output 23. This is connected to a pin for connecting to input 6. Disabling the operation of adjustable transducer 3,

The time delay circuit 28 is made on the eighth 50 and ninth 51 resistors and the second capacitor 52, the input 45 of the time delay circuit is

The cut 50 and ninth 51 resistors connected in series are connected to its output 46, and the middle point between the eighth and ninth resistors is connected to the common conductor 25 via a second capacitor 52.

The memory unit 29 is made on the first 53 and second 54 two-input AND-NE elements, the third capacitor 55 and the tenth resistor 56. The first input of the first AND-53 element is connected to the first input 47 of the memory unit, and the second input of the first AND element- NO 53 - with the output of the second element AND-NOT 54 and with the output of the 49th memory block. The output of the first element AND-NOT 53 is connected to the first input of the second element AND-NOT 54, the second input of which is connected to the common conductor 25 through the third capacitor 55, and through dec

The resistor 56 is with the second input 48 of the memory block 29.

The device works as follows.

The analog signals taken from the output of the frequency adjuster 7 and the frequency sensor 9 are fed to the input terminals 16 and 19 of the converters 10 and 11. The signal from the output of the converter 10 has the polarity of the first output of the additional power source 15. The output signal from the converter 11 has the opposite polarity. From the outputs 17 and 20 of the converters 10 and 11, the signals are fed to the inputs 18 and 21 of the comparison unit 12 through resistors 31 and 32, respectively. In the comparison block 12, the algebraic addition of the input signals taken from the outputs of the converters occurs 10 and 11. Output 26 of block 12 produces a signal that is fed to input 27 of a null organ 13. Signal received at output 44 of a null organ 13, via input terminal 45 of time delay circuit 28, controls memory block 29. The signal from the output 49 of the memory block 29 is fed to the input 6 to the inhibitor of the operation of the adjustable converter 3 of the electric drive 2, the control- drive of the executive motor 8.

In the steady state of operation, when the actual value of the rotation speed of the engine corresponds to

this, the positive signal from the output 17 of the converter 10 exceeds in absolute value the negative signal taken from the output 20 of the prevailing

razovatel 11.

0

five

At the same time, a positive signal appears at the output 26 of the comparator 12, which affects the input 27 of the null organ 13, and a positive signal is also produced at the output 44 of the nullorgan. This signal is fed through the time delay circuit 28 to the input of the memory unit 29, producing at its output 49 a single signal permitting the operation of the drive. In order to eliminate the false triggering of protection at zero signals of the frequency adjuster 7 and the frequency sensor 9 9 to the third input 22 of the comparison unit 12 via re-; The resistor 33 supplies the bias voltage from the output 23 of the auxiliary source 15. This voltage maintains the positive output level 44 of the null organ 13 and thus does not let the drive block signal

to the input of the adjustable converter

3 electric drives 2,

Simultaneously with the signal applied to the input of the comparator unit 12, the signal from the output of the converter 10 is fed to the input terminal 35 of the braking control unit 14. This signal is in phase through resistors 37-39, respectively supplied to the first and second inputs of the operational amplifier 36,

In the established operating mode of the electric drive, when the input signal taken from the output 17 of the converter 10 has a constant level, a negative signal level at the output of the operational amplifier 36 "is detected in the input resistors 37-39. At the same time, the transistor 41, the base of which is connected with the output of the operational amplifier 36, it is in the closed state and keeps the executive relay 42 in the off state. The braking control unit 14 in this case is not activated.

If, during operation, the rotational speed of the motor51 exceeds the set value determined by setting the frequency adjuster 7, the negative signal removed from the output of the converter 11 of the frequency sensor 9 exceeds the absolute value of the signal removed from the converter 10, as a result of the output of block 12 Wits si: the negative polar drive, which, acting on the input of the zero-organ 3, will cause the output 44 of the zero-organ 13 of the negative signal, This signal through the circuit 28 of the time delay deduce the output of the two-input element 54 of the memory block 29 to the zero state5 by prohibiting further operation of the reversing electric drive 2 The braking control unit 14 in this mode of operation will not change its state, since the signal level at its input will remain unchanged; the need to move to a higher speed setting, then there will be no change in the operation of the device.

If it is necessary to switch from a higher speed setpoint to a lower one, as well as to stop braking, the braking control unit 14 comes into operation to prevent a false trigger.

five

0

five

0

five

0

five

0

five

When the setpoint of the frequency reference 7 decreases, the input signal decreases at the first input of operational amplifier 36 of block 14, while at the second input the signal level is kept constant until the first capacitor 40 recharges through the sixth resistor 38 " that the level of the signal at the second input 36 until the end of the discharge of the first capacitor 40 is higher than that at the first input, the output of the operational amplifier 36 is a positive signal th layer which impact on the base of transistor 41, opens it, and includes the output relay 42. The second terminal of its last closing contact 43 connects to an input unit 30 12 Comparative positive level signal from the additional source 15 via the first terminal 43 to make contact time; necessary for braking the executive engine 8 and transition to a new setpoint speed. As a result, the output of the comparison unit 12 for the time j necessary for the transition to the new speed setpoint, prevents the emergence of a negative signal, which could cause the zero-organ switching 13 and prohibit further operation of the drive.

To prevent the protection from tripping when the actuating relay 42 is turned on and the contact 43 is closed, when a negative signal c appears at the input 27 of the null organ 13 for a short time causing a negative signal at the output 44 of the null organ 13, a time delay circuit 28 which, for the duration of the transient, keeps the input signal at the input 47 of the memory block 29 at the same level, which prevents the two-input element AND-HE 54 from being switched to the zero state.

For the initial installation of two: x; input elements AND-HE 53 and 54, the additional source 15, the third capacitor 55 and the tenth resistor 56, are supplied to the operating state

The use of the proposed device allows simple means

It is important to solve the important task for wide-range industrial electric drives to protect a reversible electric drive from exceeding the rotational speed with sufficiently high accuracy and reliability. At the same time, the cost of the security device is reduced.

Claims (3)

Invention Formula 1, Device for protection against over-rotational speed of a reversible electric drive that includes an adjustable converter with a control input, a power output and an input Disabling work, a frequency setting knob, an output connected to the control input of an adjustable converter, and an executive motor connected to the power output adjustable transducer equipped with a rotational speed sensor containing the first and second transducers, a comparison unit, a null organ, a braking control unit, and A direct current source, the first converter has an input output for connecting to the output of the speed setting device and the output is connected to the first input of the comparison unit, the second converter has an input for connecting to the output of the speed sensor, and the output is connected to the second input of the comparison unit having the third input for connecting to the first output of an additional source, the second pin being connected to the common conductor of the device, while the output of the comparator unit is connected to the input zero-o In order to improve the reliability of the protection by simplifying the device 9, a time delay circuit and a memory block are inserted into it, the first converter is made with the polarity of the output signal coinciding with the polarity of the first output of the additional source, and the second converter is with the opposite polarity of the output signal, the comparison unit is equipped with the fourth input and is made on four resistors, included in the comparison unit between the output and the corresponding input, the braking control unit in the output viewer is connected to the output of the first converter and made on the operational amplifier, the fifth, sixth, seventh resistors j the first capacitor j transistor and the executive relay with a closing contact, in the braking control unit, the input terminal of this block. through the fifth resistor is connected to the first input of the operational amplifier, and through the sixth and seventh resistors connected in series with the second input of this amplifier, the midpoint between the sixth and seventh resistors is connected through the first capacitor co5 with the conductor, the output of the operational amplifier is connected to the base of the transistor, to the collector-sump circuit of which for linking to 0 to the output of the additional source, and the actuator winding is turned on by the current lead, the first output of the closing contact of which is connected to the terminal for connection 5 to the first output of the additional source, and the second output of this contact is connected to the fourth input of the comparator unit, the output of the null organ is connected to the input of the time-delay circuit, the output connected to the first input of the memory unit, the second input of which is connected to the display - c to the first output of the additional ™ source, and the output of the power supply unit is connected to the output for connection to the control panel to prohibit the operation of the adjustable converter, 2. The device according to claim 1, about tl and the fact that the time delay circuit is made on the eighth and ninth resistors and the second capacitor, and the input of the time delay circuit is connected to its output through serially connected eighth and ninth resistors and the middle point between the eighth and ninth resistors is connected via a second capacitor to a common conductor. 3. The device according to claim 1, about t l. P This is accomplished in that the memory block is implemented on the first and second double-ended IS-NOT elements, the third capacitor and the tenth resistor, with the first input of the first AND-NO element connected to the first input of the memory unit, the second input of the first AND-NOT element connected to the output of the second element, AND-NOT and to the output of the memory block, the output five five 91 03209, Q The first element of the NAND is connected to a capacitor connected to the common current input of the second NAND, water, and through the tenth resistor to the second input of which through the third to the second input of the memory unit.