SU1397841A1 - Device for automatic selection of measuring limits of digital instruments - Google Patents

Abstract

The invention relates to a measurement technique and can be used in digital measuring instruments for the automatic selection of measurement limits. The device for automatic selection of measurement limits of digital devices contains a pulse counter, triggers 3-5, a reversible counter 8, a pulse generator 9, a frequency divider 10, an OR 6 element, a pulse former 7, counters I, 2. The device has an increased speed. 3 il.

Description

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The invention relates to a measurement technique and can be used in digital measuring instruments for the automatic selection of measurement limits.

The purpose of the invention is to increase the speed of the device.

FIG. Figure 1 shows a block diagram of a device for automatically selecting the limits of measurement of digital devices; in fig. 2 and 3 are diagrams that show his work.

The device (Fig. 1) contains counters 1 and 2, triggers 3-5, a series-connected element OR 6, a driver 7 pulses and a reversible counter 8, series-connected pulse generator 9 and a frequency divider 10.

The device operates as follows.

The frequency fx is input to the device, is proportional to the measured value, and from the frequency divider outputs are received the frequency

tots f, and f. respectively, on the set- ting and automatic selection device, the input input of the counter 1 and the counting input of the count- 0 Dealer digital measurements of the device 2, and the counters 1 and 2 have the conversion factors Ki and K2. The conditions for the presence of pulses at the outputs of counters 1 and 2 are attenuator attenuators, and can be adjustable.

When the frequency f is found in zone I (Fig. 2), the pulse from the output of counter 2 (Fig. 3d) resets trigger 3 (Fig. 36), causing the subtraction mode of the reversible counter 8, and sets trigger one to 5 (Fig. Ze ). The logic level "1 comes from its output to the pulse shaper 7 through the element OR 6, and a short pulse is generated, resetting trigger 5 (Fig. Зж) and decreasing by one the value of the content of the reversing counter 5. When the frequency fx is in the zone I (FIG 2) the content of the reversible counter 8 does not change.

Claims (1)

Invention Formula are ki one, thirty If the pulse frequency fx is in zone III (Fig. 2), then the pulse from the output of counter 1 (Fig. For) sets the triggers 3 and 4 into the unit state (Fig. 3b, c), while the control input of the reversible counter 8 receives the logical level "1, causing the summation mode. Logical level "1 from the trigger output 4 through the element OR 6 enters the pulse shaper 7, which forms a short pulse (Fig. 3g), resetting the trigger 4 and increasing by one the contents of the reversing counter 8. Pulse delay from the output of the pulse shaper 7 relative to the front of the signal from the trigger output 4 by time t ( Fig. 3g) is due to the inertia time of the device, including the speed A pulse counter, the output of which is connected to the first input of the first trigger, the output of which is connected to the control input of the reversible counter, the second trigger, characterized in that, in order to increase the speed of the device, a series-connected pulse generator, frequency divider, second counter, and third trigger are introduced , the OR element and the pulse shaper, the first input of the first trigger is connected to the first input of the second trigger, the output of which is connected to the second input of the OR element, the output of the driver pulses are connected to the counting input of a reversible counter and the second inputs of the second and third flip-flops, output 35 of the second counter is connected to the second input of the first trigger, and the device's input is connected to the counting input of the first counter and to the installation input of the second counter, and the second output of the splitter frequency is connected to the input of the installation in “About the first counter. Closer attenuator, and can be adjustable. When the frequency f is found in zone I (Fig. 2), the pulse from the output of counter 2 (Fig. 3d) resets trigger 3 (Fig. 36), causing the subtraction mode of the reversible counter 8, and sets trigger one to 5 (Fig. Ze ). The logic level "1 comes from its output to the pulse shaper 7 through the element OR 6, and a short pulse is generated, resetting trigger 5 (Fig. Зж) and decreasing by one the value of the content of the reversing counter 5. When the frequency fx is in the zone I (FIG 2) the content of the reversible counter 8 does not change. Invention Formula The device for automatic selection of pre-Delov measurements of digital devices contains A pulse counter, the output of which is connected to the first input of the first trigger, the output of which is connected to the control input of the reversible counter, the second trigger, characterized in that, in order to increase the speed of the device, a series-connected pulse generator, frequency divider, second counter, and third trigger are introduced , the OR element and the pulse shaper, the first input of the first trigger is connected to the first input of the second trigger, the output of which is connected to the second input of the OR element, the output of the driver pulses are connected to the counting input of the reversible counter and the second inputs of the second and third triggers, the output of the second counter is connected to the second input of the first trigger, and the device input is connected to the counting input of the first counter and to the installation input of the second counter, and the second output of the frequency divider connected to the installation input in “About the first counter. but F | Fig.Z