SU1387019A1 - Device for extracting signal absolute value - Google Patents

Abstract

The invention relates to devices for the allocation of an electrical signal module and can be used in analog computers. The aim of the invention is to increase accuracy. The device for absolute signal magnitude contains input 1,. Amplification unit 2 with aphasic output pairs, first and second rectifying transistors 3 and 4, buffer amplifier 5, current generator 6, output 7, first and second load resistors 8 and 9, first and second amplifying transistors 10 and 11, reference source 12 voltages, first and second power buses 13 and 14. The operation of the device is based on splitting the signal from input 1 into two antiphase signals, redistributing the jroKa generator 6 between the first and second. Simultaneous transistors 3 and 4 depending on the polarity of the signal from input 1 and stabilization of the value of the currents using the first and second amplifying transistors 10 and 11. 1 sludge. from S to 00 00 with

Description

The invention relates to devices for the allocation of an electrical signal module, and can be used in at-logic computing.

The aim of the invention is to improve the accuracy.

The drawing shows a functional diagram of the device for determining the absolute value of the signal.

The device contains input 1, an amplifying unit 2 with paraphase outputs, Perv 3 and Second A supra-transistors, buffer amplifier 5, Current generator 6, output 7, first 8 and second 9 load resistors, Perv 10 and second 11 amplifying transistors , the source 12 of the reference voltage, the first 13 and the second 14 power supply tires.

A device for extracting an absolute value of a signal operates as follows.

Let the signal at input 1 exceed 50 mV. If the signal at input 1 grows to the positive side, then the first transistor 3 is open, and the second rectifier transistor 4 is closed. Then the voltage drop across the second load resistor 9 is absent, j junction base-emitter of the second amplifying transistor 11 is shifted in the opposite direction. This means that the second amplifier transistor 11 is closed, the current does not flow through it, therefore the current of current generator 6 is redistributed between the first rectifier transistor 3 and the first amplifier transistor 10, the current through the first high transistor 3 is maintained with high accuracy at positive growth due to the stabilizing effect of the first amplifying transistor 10. I

Similarly, when the input voltage rises towards negative values exceeding the absolute value of 50 mV, the first transistor 3 and the first amplifying transistor 10 are closed, and no currents flow through them. The second high-voltage transistor 4 and the second amplifying transistor 11 are open,

The first 10 and second 11 amplifying transistors should be the same in parameters and the first and second rectifying transistors 3 and 4 should also be the same

parameters. Then the current through the second high-power transistor 4 is maintained with high accuracy by the stabilizing effect of the second amplifying transistor 11,

i

With input voltage values of 1 lying in the range of 0-50 mV, first 3 and second. 4 rectifying transistors and the first 10 and the next 11

amplifying transistors open. The currents flowing through the first 3 and second 4 rectifying transistors are kept within the specified limits due to the stabilizing effect

first 10 and second 11. amplifier transistors.

Claims (1)

Invention Formula A device for isolating the absolute value of a signal, containing an amplifier with paraphase outputs, whose input is the device input, first and second rectifying transistors, whose emitters are connected to the input buffer amplifier and to the first output of the current generator, the second output of which is connected to negative bus power supply, the base of the first and second rectifying transistors are connected respectively to the first and second outputs of the amplifier unit with paraphase outputs, the output A buffer amplifier is an output of a device, characterized in that, in order to improve accuracy, the first and second elements with non-linearity of the cut-off type, implemented respectively on the first and second amplifying transistors, the first and second load resistors and the reference voltage source The first terminal of the first load resistor and the base of the first amplifying transistor are connected to the collector of the first fast-moving transistor, to the collector of the second fast transistor zistor connected to the cert the second load resistor and the base of the second amplifying transistor; the second leads of the first and second load resistors are connected to 3. 1387019. . . The positive bus of the power source, the amplifier amplifiers transistors, the count of the source of the reference voltage, the lecturers of which are connected to the input are connected to the emitters of the first and second buffer devices.