SU1387018A1 - Programming language translator - Google Patents

Description

(89) BG 33401 / BG 46425 / 31.01.80 148) 30.09.80

(21) 7772150 / 24-24

(22) 12.11.81

(46 P7.04.88. Bull. No. 13 (71) SMEHES Lenin (BG) (.72) Bonn Yankov Yankov and Lil n Iliev Nikolov (BG)

(53) 68J.325 (088.8)

(54) LANGUAGE TRANSLATOR PROGRAM 1 WORLDWIDE

(57) The invention relates to computing and is intended for hardware translation of programming languages. The purpose of the invention is to expand the functionality of a translator by translating various languages of an arbitrary design. The transmitter contains block 1 of firmware control, input and input counters.

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3, 4, counter 5 of the address of the current character, block 6 of the operative memory of the current symbol, counter 9 of the internal label, counter 10 of the intermediate result, reversible counter of the operands 13 and operators 17, register 20 of the address, block 7 of the fixed memory of the rule translation, counter 8 addresses of the translation rule, block of registers of stack memory of operands 11 and operators 15, blocks of stack memory of operands 12 and operators 16, multiplexer of operands 14, decoder of 18 operators, block 19 of permanent memory of the function of the preceding one, two registers 21, 22 function preceding comparison circuit 23 and current character register 24. The exchange between the blocks is carried out via bus 2 of data according to the corresponding control signals of block 1. 6 Il.

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The invention relates to computing and can be used for hardware translation of programming languages.

A computing device is known that allows programming languages to be translated mainly by software (UK Application No. 1407761, Cl. G 06 F 15/20, .1975).

However, the device has a low translation speed of programs written in problem-oriented languages, since the use of programs for translation degrades the speed of translation.

The closest in technical essence to the invention is a device comprising a firmware control block, an input counter, an output counter, a current symbol address counter, a current character memory block, an internal label counter, an intermediate result counter, reversible operand counters and operators and register the addresses, and the output of the current character address counter is connected to the address input of the operating memory block of the current character (USSR Copyright Certificate No. 674028, Cl. G 06 F 15/38, 1976).

A disadvantage of the known device is that it does not allow changing input and output languages, i.e. implement translation of several languages on the same hardware. In addition, using the device can only translate expressions in high-level languages.

The aim of the invention is to extend the functionality by translating various languages of an arbitrary design.

This goal is achieved by reconfiguring the translator to work with various input and object languages by changing the contents of the permanent storage devices.

Fig. 1 shows a functional diagram of the translator in Fig. 2 - encoding of internal symbols on the input tape, where the operator stands for, C is its code, and 1 is rand, with C being a pointer in the name or constant table} in Fig. . 3 - character encoding in step 0

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operand memory, where P is a pointer, is a terminal, and is a non-terminal; in fig. 4 - character encoding in the memory of the translation rules, where C is a code or pointer, and TT bits encode the type as follows: - terminal, - nonterminal, - internal label, and - - intermediate result; Fig. 5 illustrates the encoding of characters on the output tape, which is similar to that indicated in Figs 2 and 3; in fig. 6 - the register is functional - the current character.

The translator (Fig. 1) contains block 1 of firmware control, data bus 2, input 3 and output 4. counters, counter 5 of the address of the current character, block 6 of the operational memory of the current symbol-, block 7 of the permanent memory of translation rules the counter, the address 8 address 1 of the translational rule, the counter 9 of the internal label, the counter 10 of the intermediate result, the operand stack composed of the block 11 of the operand stack memory registers and the block 12 of the memory; operands, reversible counter 13 operands, multiplexer 14 operands, operator stack, composed of block 15 registers of operator memory and block 16 of operator stack, reversible counter — 17 operators, decoder of 18 operators, block 19 of the previous memory function, the address register 20, the first 21 and second 22 function registers of the preceding, comparison circuit 23, the current symbol register 24, and the inputs of the reversible counters of operands 13 and operators 17 are connected to the address inputs of the stack memory operand There are 12 operators and 16, respectively, the informational inputs-outputs of which are connected to the first informational inputs-outputs of the blocks of registers of the stack memory of operands 11 and operators 15, respectively, whose information outputs are connected to the information inputs of the multiplexer 14 operands and the decoder 18 operators, respectively, the counter output The 8 addresses of the translation rule are connected to the address input of the block 7 of the permanent memory of the translation rules, the output of which is connected via data bus 2 to the information input of register 24 its symbol, the first output of which is connected to the address input of the multiplexer 14. operands, the output of which is connected via bus 2 data to the information input of the operating memory block 6 of the current character, whose information output is connected via bus 2 data to the information inputs of the input counter 3, output counter 4, to the information input of the register 24 of the current symbol, the second information output of which is connected via the data bus 2 to the information input of the RAM 6 of the current character 6, with the second information units of the registers of the stack memory of operands 11 and the stack memory of operators 15 and with the information input of the register 20 of the address, the output of which is connected to the address input of the block 19 of the permanent memory of the function preceding, the output of which is connected to the information inputs of the first 21 and second 22 function registers

: preceding, the outputs of which are connected to the first and second informational inputs of the comparison circuit 23, the output 68 of which, the output signs of filling the blocks of registers of the stack memory of operands 48 and the stack memory of operators 58, the outputs of the bits of the prg what type of character 73 and 74 and zero: the current state of the current character register is connected to the corresponding inputs of the logic conditions of the microprogramming unit 1, the output of the decoder 18 operators is connected via the data bus 2 to the information input of the counter 8 of the translation rule, moves counter internal label 9

and intermediate result 10 are connected via bus 2 data to the information input of the register 24 of the current symbol, the input input 3 and v2.

input 4 counters are connected via bus 2 data to the information input of counter 5 of the address of the current symbol, output-output counter is connected via bus 2 data to the second information input-output of block 11 of operand stack memory registers, second information input-output of block 15 of registers of stack memory These operators are connected via bus 2 data to the information input of the register, 20 addresses, recording entries 25 and 28, outputs 26 and 29 and counting inputs 27 and 30 of input counter 3 and output account

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4, respectively, input 31 of the initial installation, input 32 of the record and counting input 33 of the counter 5 of the address of the current character, input 34 of the read control and input 35 of the operating memory 6 of the current character, read inputs 36 and 64 of the permanent translation memory 7 and the functions preceding 19, entry entry 37 and counting input 38 of counter 8 of the translation rule address, inputs of initial setup 39 and 42, inputs 40 and 43 of resolution permissions, and counting inputs 41 and 44 of counters of internal tag 9 and intermediate result 10, respectively, installation inputs in О 50 and 60, counting summing 51 and 61 and subtracting 52 and 62 inputs of reversible counters of operands 13 and operators 17, respectively, write control inputs by reading 49 and 59 memory blocks of operands 12 and operators 16, multiplexing, copy permit 53 inputs operands and decoder 18. operators, inputs 65, 66, and 67 of the register of address 20, the first 21 and second 22 of the preceding function registers, installation inputs of O 45 and 54, write 46 and 55, read 47 and 56 blocks of registers of the stack memory of operands 11 and operators 15, respectively , the permission input for issuing 57 block of operators' stack memory registers 15, recording entries 69, issuing permissions 71 and all the features of character type 72 of register 24 of the current character are connected to the corresponding control outputs of firmware control unit 1. Thus, the structure of the translator is open (open) and each block can be connected to the rest via bus 2 data.

The current symbol register 24 contains a counter 76 in which field C is placed, triggers 77 and 78 in which characters of the TT character type are written, a counter zero state decoder 79, buffers 80 and 81 with three states, an OR element 82, and the information input of the register 24 of the current symbol is composed of information inputs of the counter 76 and flip-flops 77 and 78, the output of the counter 76 is the first information output of the register 24 and it is connected to the input of the zero state decoder 79, to the information inputs of the buffer 80 and the multiplexer 14 trigger 77 is connected to information input of buffer 81, outputs of buffers VO and 81 make up the second information output of register 24 of the current symbol, record 69 is connected to the corresponding inputs of counter 76 and triggers 77 and 78, input 71 decreases by one is connected to the subtracting counting input of counter 76, the issue resolution input 70 is connected to the corresponding inputs of the buffer 80 and through the OR 82 element of the buffer 81, the input 72 of the resolution of the character type indicator is connected via the WL 82 element to the corresponding input of the buffer 81.

The translator works as follows.

At the start of the translator, the initialization is carried out, at which the initial installation of the counters 5, 9, 10, 13 and 17 and the register blocks 11 and 15 is carried out, and from the microprogram control unit 1 the corresponding control signals are fed to the inputs 31, 39, 42, 45, 50, 54 and 60. After that, the address of the source program, which is the input tape of the translator, is written into the input counter 3, and the output address 4, where the object program generated by the translator must move, i.e. output translator tape. This is done by applying to the inputs 34 and 35 of the operating memory 6 of the current symbol of the read signals 34 and selecting 35, the read information at the address contained in the counter 5 of the address of the current symbol is recorded via bus 2 data into the input counter 3 by applying a signal to its input is 25. The content of counter 5 is increased by one (from block 1 a signal is received at input 33) and information from block 6 of operational memory is read and information is recorded into output counter 4 by applying a signal to its input 28.

The reading, analysis and translation of the source program begin. The content of the input counter 3 is transmitted via the bus 2 data to the counter 5 addresses of the current symbol, and the control signals to the inputs 26- and 32 are fed, is read to the corresponding address of the block 6 operational

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the memory of the current character from the input tape (control signals are fed to inputs 34 and 35 of block 6), which is sent via data bus 2 to register 24 of the current character by applying a signal to input 69.

Firmware control block 1 analyzes the current symbol - its. field T, which is a logical condition 74, and depending on its type, implements some of the following actions,

If an operand () character is typed, it is written to the operand stack as follows. The firmware control unit 1 analyzes the state of the sign 48 - Full register. If the logic is O, then block 1 sends control signals 46 and 70, and the contents of registers 24 will be written to the upper limit of the symbol in the uppermost register of block 11 of registers, and the P field will be set to 1. If logical 1, i.e. the register block 11 is full, then the output .. the contents from the lower register register block 11 is recorded in the continuation of the stack memory - memory block 12 by applying a signal from input 1 of the microprogram control to input 49, after which the content of counter 13 is increased by unit (a signal is fed to its input 51). The control signal from block 1 is now supplied to the input 27 of the counter 3, as a result of which its content is increased by one and the indicated actions are repeated for reading and analyzing the current symbol.

If an operator-type character (), the address defined by the code in register 24 of the current character (after C) is written to address register 20 (control block receives control signals to inputs 65 and 70 from block 1), and then a read signal is sent to input 64 of block 19 is a permanent memory of the function preceding. The read information is a function preceding the comparative priority of the current symbol AND is written into the first register 21 of the function preceding by supplying a control signal to its input 65. After that, the upper character of the stack memory is read from the top register of the block 15 and sent to the address register 20 (for this purpose, block 1 sends control

signals to inputs 57 and 65). At the corresponding address from the constant memory block 19, the function preceding is read - the comparative priority of the upper character in the stack memory (a control signal arrives at read input 64) and is written to the second register 22 of the function preceding 22 (block 1 delivers a control signal at the input 67). The contents of registers 21 and 22 are compared by combinational means by means of circuit 23 and, depending on the result — feature 68, one of the following actions is carried out.

a) If the content of the first register 21 of the function preceding is greater than the content of the second register 22, i.e. the value of feature 68 is logical 1, then the current character of register 24 is written in the operator stack as follows. The firmware control unit .1 analyzes the state of feature 58 of the full register block. If it is logical O, then block 1 sends control signals to inputs 55 and 70 and the contents of register 24 of the current character is written to the uppermost register of block 15, and at the same time information is transmitted between the following registers. If the attribute has a logical value of 1, i.e. the block 15 is full, the content leaving the lower register of the block 15 is written in continuation of the stack — block 16 by supplying the control signal from the block 1 to the read control input 59, after which the content of the counter 17 is increased by one (block 1 sends a signal to input 61). This is followed by an increase in the content of the input counter 3 per unit (block 1 provides a signal to input 27) and a transition to the indicated actions on reading and analyzing the following symbol: from the input tape.

b) If the contents of the first 21 and second 22 registers of the preceding function are equal to each other (the value at output 68 is logical 1), then proceed as per item a.

c) If the content of the first register 21 of the function preceding is less than the content of the second register 22 - the state of the sign 68 is logical O,

This is translated by transl.

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The chi, which is as follows: the source code generated by the operator decoder 18 is sent via data bus 2 to the counter 8 of the translation rule address (control signals from inputs 37 and 63 arrive from the microprogram control unit 1). This code defines the starting address of the translation rule. Starting with the address specified by counter 8, the characters of the translational rule are counted one by one from block 7 (until the end of the rule character is found), and for reading each next character, the content of the counter 8 of the translation rule address is preliminarily increased by one. The read character is sent to the current character register 24. To perform these actions, microprogram control unit 1 sends control signals to inputs 36 and 69, and then sends a signal to input 38. The character type in register 24 is analyzed by microprogram control unit 1 — the values of features 73 and 74 (field TT) and Depending on its type, one of the following actions is performed.

If this type of terminal, it is sent by register 24 of the current character to block 6 at the address specified by output counter 4 as follows. The contents of output counter 4 are transferred to counter 5, and from the microprogram control unit 1, control signals are sent to inputs 29 and 32. Control signals are then sent to inputs 70, 34 and 35, with the result that the contents of register 24 of the current symbol are written into the block 6. Finally, the content of the output counter 4 is increased, and a control signal is applied to its input 30. Thus, the character is recorded on the output tape. Go to reading and analyzing the next character of the translation rule.

If this type is non-terminal, then by this method the address from output counter 4 is recorded in counter 5, and in block 6 the content of the k-ro register of block 11 of the operand stack memory registers, where k is the pointer located in the field C of register 24 of the current character. Register selection is controlled by multiplexer 14 operands.

Applying the control signals to the inputs 53, 34 and 35 results in writing the contents of the selected register in block 6. We return to reading and analyzing the next character of the translational rule.

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an internal symbol is first formed as follows. The content of counter mark 9 or counter 10 of the intermediate result, respectively, is written to the current symbol register 24 (field C), control signals are fed to inputs 40 or 43 and 69 for this purpose. After that, the internal symbol is recorded on the output tape; in block 6 at the address determined by the output counter 4 in this way. Finally, the output counter 4, the internal tag counter 9 (or the intermediate result counter 10) are increased by supplying control signals to the inputs 30, 41, or 44, respectively.

Then proceed again to reading and analyzing the next character from the translational rule.

If it is the End of a Rule character, then M-characters are pushed out of the operator stack, where M is determined by the next in order character of the translation rule. K-symbols are pushed out of the stack memory of operands, where K is determined following the M-symbol read from the persistent memory block 7 of the translation rule. This is done as follows. In this way, from block 7 of the permanent memory, the translation rules are read and written to register 24 of the current symbol of the sym., Wave. After that, the content of the counter 8 of the translation rule address increases by one. The ejection of characters from the stack of operator memory is carried out as follows. The keeping of the reversible counter 17 is reduced by one (a control signal is applied to input 62), the element recorded at the top of the stack memory — the uppermost register of the stack of 15 registers of the 55 memory — is removed. these aperators by supplying control signals to inputs 56 and 59, with the information moving up

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between the registers, and the element of the block 16 of the operator stack, indicated by the reversible counter 17, is written to the lowermost register of the block 15. The content of the field C of the register 24 of the current symbol is decreasing. supplying a control signal to input 71, after which it is checked whether its content is zero (sign 75). If this is not zero, then the specified actions to push elements out of the operator stack memory are repeated. In the opposite case, the next character K is read from block 6 and written to register 24 of the current character. The characters are pushed out of the operand stack. The content of the reversible counter 13 is reduced. per unit (microprogram control unit 1 sends a control signal to input 52), then control signals to inputs 47 and 49 are received, which pushes the symbol from the top of the stack memory (the uppermost register of the operand stack memory register 11), and an element of the operand memory block 12, indicated by the reversible counter 13, is written in the lowermost register of the block 11. The content of the field C of the register 24 of the current character is reduced and it is checked whether its content is zero. If it is not zero, then the specified actions for pushing a symbol from the stack memory of operands 11 are repeated, an operand type symbol and a pointer equal to the current content of output counter 4 are written. For this purpose, control signals are fed to the microprogram control unit 1 29 (issuance to counter 4 is permitted), 72 (allowance is allowed for register 24 - field T) and 46 (entry 11). Start reading the next character from the input tape and analyzing its type. By this the translator cycle is closed.

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Claims (1)

50 claims Programming language translator containing firmware control block 1, input counter 3, output counter 4, current character address 5 counter, current character memory block 6, internal label counter 9, intermediate result counter 10, reversible counter of operands 13, reversible counter operators 17, the address register 20, the output of the address counter of the current character 5 is connected to the address input of the operative memory block of the current character 6, so as to expand the functionality of the trans Lists are translated due to the translation of different languages of arbitrary design, a fixed memory block of translation rules 7, an address counter of translation rule 8, a stack memory register of operands 11, a stack memory of operands 12, a multiplexer of operands 14 are entered into it, block of registers of stack memory of operators 15, block of memory of operators 16, decoder of operators 18, block of fixed memory of function of preceding 19, first and second registers of function of preceding 21 and 22, comparison circuit 23, register of current symbol 24, outputs of reversible counters Operands 13 and operators 17 are connected to address inputs of memory blocks of operands 12 and operators 16, respectively, information inputs / outputs of which are connected to the first information inputs / outputs of stack register registers of operands 11 and operator stack 15, respectively, whose output outputs are connected to the information inputs of the multiplexer operands 14 and the decoder 18 operators, respectively, the output of the translation rule 8 address counter is connected to the address input of the rule memory block. 7, the output of which is connected via the data bus 2 to the information input of the current symbol register.24, the first output of which is connected to the input of the multiplexer operands 14, the output of which is connected via the data bus 2 to the information input of the operational symbol of the current symbol 6, information output which is connected via the data bus 2 to the information inputs of the input counter 3, the output counter 4 and the register the current symbol 24, the second information output of which is connected via the data bus 2 nd to the information input of the operating memory block of the current symbol 6, to the second information inputs / outputs of the blocks register g 5 0 5 l j 0  . 0 The stack memory of operands 11 and the stack memory of operators 15 and to the information input of the address register 20, the output of which is connected to the address input of the block of the previous memory function 19, the output of which is connected to the information inputs of the first 21 and second 22 registers of the function preceding, the outputs of which are connected to the first and second information inputs of the comparison circuit 23, the output of which 68, the output of the signs of filling the blocks of registers of the stack memory of operands 48 and the stack of operators 58, the outputs of the signs of the character type 73 and 74 and the zero state 72 of the register of the current symbol 24 are connected to the corresponding inputs of the logic conditions of the microprogram control unit 1, the output of the operator decoder 18 is connected via the data bus 2 to the information input of the translation rule address counter 8, the outputs of the internal tag counter 9 and the intermediate counter Result 10 is connected via the data bus 2 to the information input of the register of the current symbol 24, the outputs of the input counter 3 and output counter 4 are connected via the data bus 2 to the information input of the account the address of the current character 5, the output of the output counter 4 is connected via the data bus 2 to the second information input / output of the stack memory register block, operands 11, the second information input / output of the stack register memory block of operators 15 is connected, via the data bus 2 to the information the input of the address register 20, the write inputs 25 and 28, the output permissions 26 and 29 and the summing counting inputs 27 and 30 of the input counter 3 and the output counter 4, the input of the initial installation 31, the input input 32, the sum of the current counter 33 symbol 5, read control input 34 and input 35 of the current block of the current symbol 6, read inputs 36 and 64 of the permanent memory blocks of the translation rules 7 and the function preceding 19, write input 37 and the summing count input 38 of the address counter translation rules 8, the inputs of the initial installation 39 and 42, the inputs of the resolution of the issue 40 and 43 and summing the counting inputs 41 and 44 of the counters internal labels 9 and intermediate result 10, installation inputs in O 50 and 60, summing counting inputs 51 and 61 and subtracting counting inputs 52 and 62 of reversible counters of operands 13 and operators, write control inputs: reading 49 and 59 of the stack memory of operands 12 and stack memory of operators 16, inputs for enabling the multiplexer output of operands 53 and operator decoder 18, write entries 65, 66, 67 of address register 20, first and second registers 21, 22 (PU2.2 cpuz.3 the forerun functions, installation inputs in O 45 and 54, records 46 and 55 and 47 and 56 from the 47 and 56 blocks of the stack memory registers of operands 11 and the stack of operators 15, resolution permission 57 of the stack modules of operators stack 15, write inputs 69 , issuance permission 70, decrementing by unit 71, and permitting issuance of a type of register character of the current symbol 24 are connected to the corresponding outputs of the firmware control unit 1. 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