SU1385322A2 - Device for receiving signals with frequency-phase modulation - Google Patents

Abstract

The invention relates to radio information transmission. The purpose of the invention is to improve noise immunity. The device contains a frequency detector I, a delay line 2, integrators 3, 9, a block for selecting the non-moon, a grid of frequencies, a key 6, a phase detector 7, an ADC 8 and 10. The blocks 11 and 16 are clocked, amplitude detectors 12 and 17, comparator 13, key 14, block 15 frequency control. At the outputs of the A / D converters 8 and 10, information flows are received, transmitted by frequency and phase subchannels. The streams arrive at blocks 11 and 16, to-rye allocate clock signals (TC) (block 11 - TC, extracted from the frequency subchannel, block 16, of the phase). These vehicles arrive at detectors 12 and 17, to-rye allocate enveloping vehicles. Comparator 13 compares the levels of the vehicle envelopes. The control signal from comparator 13 sets the key 14 to the state corresponding to the passage of the output of the last vehicle having a higher level. This vehicle enters the block 15, to-ry produces on it the adjustment of the internal clock Mr.. The g-signal from the output of block 15 is fed to the additional inputs of integrators 3, 9 and A / D converters 8, 10, and can also be used to synchronize devices in further processing of information. signals. 1 il. E cl

Description

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Line 2 of the delay produces a delay in the CTM signal by time tj equal to the duration of processing one element of the signal in the frequency subchannel until a decision is made about the frequency of this signal element as a code from the output of the first analog-digital converter (ADC) 8. Delayed by time 1, the signal enters the input of the block 4 of the carrier. In this block, the frequency of the reference oscillator. The invention relates to radio systems of transmission and transmission, can be used in the construction of high-speed systems for the transmission of discrete information.

The aim of the invention is noBbiujeHHe noise immunity.

The drawing shows a structural electrical circuit of the device for receiving signals with frequency-phase modulation.

A device for receiving signals from a frequency is placed at the carrier frequency of the signal and this phase modulation contains the frequency input to the generator 5 of the frequency grid, the detector 1, the delay line 2, which first converts this oscillation to the third integrator 3, block 4 selections of nonstop oscillations having frequencies of all possible frequencies, frequency grid generator 5, key 6, feasible (allowed) received elec- tric detector 7, the first signal aif-pyroscopic signal. These n oscillations form a transducer 8, a second integrator a grid of reference frequencies needed for 9, a second analog-digital transform-coherent reception in the phase, subchannel, tel 10, the first block i 1 clock synchronized. These reference oscillations arrive at the descent, the first the amplitude detector 12, the signal inputs of the key b, which is under the comparator 13, the additional key 14, by the influence of the frequency adjustment coming to its control - unit 15, the second block 20 of the luminous code input passes to the input of the 16 clock synchronization, the second amplitude etektora 7 with the reference oscillation detector chas- tudny 17.totoy equal to the frequency input to the

A device for receiving signals from a time-different input of the phase detector 7 of the element using total-phase modulation operates the following signal. At the output of the phases of the rho detector, a voltage is formed.25. The voltage, which is the functional input of the device, is supplied with the phase difference of the received and reference frequency-phase modulation (FMF), having

the following species; U ,,, F (Ch.-Ch op).

t

S (t) ASin ty; t-f bw (t) dt-f- "Y (t), This voltage is allocated second

where A is the amplitude of the signal envelope by the tagrator 9 and is fed to the input of the second; U; - circular frequency and initial

ofaza carrier-vibrations;

l "I) is the law of change in the frequency of the carrier oscillation; utfHV-law of signal phase change. 35 streams transmitted, respectively.

From the input of the device, the FMF signal is applied to the frequency and phase channels. It goes to the input of the frequency detector I and the data flow of data is received by 2 delays. At the output of the frequency, respectively, the inputs of the first II and second detector 1 according to the results of receiving an element of the 16th clock signal synchronization block for the clock time interval for- (BTS). The BTS data produces the selection of the measured voltage, which is from the information signals corresponding to the function of the deviation of the frequency of the received clock signals (the first BTS II - the fifth element of the signal fj from the frequency of the time signal extracted from the frequency detector of the frequency detector subchannel, the second VTS 16 - clock

Ue 0 (f G). Signal extracted from the phase train. This voltage is integrated over time. 45 ™ act signals arrive at the beat of the first integrator 3, the transfer first and second; the amplitude of which is determined by the expression

4 (t) i - ju ,, (,

where T is the integrator time constant. The voltage from the output of the first integrator 3 is fed to the input of the first analog-digital converter 8, which is pre-;

forms the voltage in the code, the corresponding level, leagues. tMinaji the current frequency of the received element is fed to the input of the frequency signal adjusting unit. This code is issued to the first 15 of the unit, which produces a device output (frequency output adjustment; internal clock generator setting. Ktnala). Clock signal from the output of the dark ADC 10, which converts it to a code corresponding to the phase of the received signal element.

Thus, at the outputs of the first 8 and second 10 ADCs, information sounders 12 and 17 are obtained, which select the envelopes of the clock signals. Comparator 13 compares the levels of clock envelopes.

The control signal from the output of the comparator 13 sets the additional key 14 to the state corresponding to the passage to the input of the last signal, which has a higher level at a given time. This clock signal

1385322

Line 2 of the delay produces a delay in the CTM signal by time tj equal to the duration of processing one element of the signal in the frequency subchannel until a decision is made about the frequency of this signal element as a code from the output of the first analog-digital converter (ADC) 8. Delayed by time 1, the signal enters the input of the block 4 of the carrier. In this block, the frequency of the reference oscillator is found by a tagger 9 and is fed to the input of the second streams transmitted, respectively.

A / D converter 10, which converts it to the code corresponding to the phase of the received signal element.

Thus, at the outputs of the first 8 and second 10 ADCs, information is received ™ on the corresponding signals to the corresponding first and second; amplitude

level and leagues tMinaji is fed to the input of a frequency control block 15, which produces an under-construction of an internal clock generator. The clock signal from the output is blob detectors 12 and 17, which select the clock envelopes. Comparator 13 compares the levels of clock envelopes.

The control signal from the output of the comparator 13 sets the additional key 14 to the state corresponding to the passage to the input of the last signal, which has a higher level at a given time. This clock signal

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The frequency control 15 receives the additional inputs of integrators 3 and 9 and frequencies, as well as sequentially connected ADC 8 and 10, to the additional key and the tuning unit, and also the second clock synchronization unit can be used to synchronize further devices and the second amplitude detector, the output of the co-processing of information signals. the second is connected to the second input of the computer, the outputs of the first and second blocks

Claims (1)

The invention of the clock synchronization is connected respectively to the second and third inputs of an additional unit for receiving signals from a partial key, the inputs of the first and second total-phase modulation according to the author. St. Clock synchronization blocks, no. 1262744, characterized in that, for the purpose of 10, to the outputs, respectively, nepBOJ-o and second, increase noise immunity due to reliable analog-to-digital converters, to determine the reliability of clock synchronization- output of the frequency adjustment block of the connection, introduced in series with the clock inputs of the first and second in-first clock synchronization unit, the recorders and the first and second analog amplitude detector, comparator,. digital converters.