SU1381603A1 - Analog memory - Google Patents

Abstract

The invention relates to computing technology, namely, storage devices, and coins to be used for sampling, storing and switching discrete values of time varying voltages generated by a plurality of measurement converters during dynamic testing of complex technical objects, or generated during technological tests. or computational processes. The purpose of the invention — improving the speed — is achieved by introducing additional comparators, the second element AND, and the block of elements I. The device provides for sampling and storing discrete values of channel voltages not successively within a single sampling step.

Description

OS

wasp

but

with W

13th

by channel number, and sequentially by channel voltage values, starting with the lowest of all and ending with the highest - during the charging phase of capacitor 5, and when discharging capacitor 5 - starting with the largest of all and ending with the lowest. The formation of channel voltages is carried out by comparators 10, formers 11 and 12 impulses.

The elements 13 and 14 are controlled. The keys 3 and 4 are controlled from the outputs of the elements 13 and 14, and the comparators 10 are controlled by the levels of logic signals taken from the output of the comparators 8 and 9, obtained by comparing the output voltage of the operational amplifier 6 and the reference voltages. stress 2 Il.

one

The invention relates to computing technology, namely, storage devices, and can be used for sampling, storing and switching discrete values of time measurements of voltages generated by a plurality of transducers during dynamic tests of complex technical objects, or generated during technological operations. or computational processes.

The purpose of the invention is to increase the speed of the device.

Figure 1 shows the functional diagram of the device; figure 2 - timing charts, c with his work.

The device contains passive elements on resistors 1 and 2, keys 3 and 4, a cumulative element on a capacitor 5, an operational amplifier 6, a clock generator 7, additional comparators 8 and 9, the main comparators 10, drivers 1 1 and 12 and fflylykov, the first element 13, second element 14, block 15 of elements i, buses 16 and 17 of positive and negative voltage, information inputs 18 of the device, inputs 19 and 20 of the reference voltages, information output 21 of the device, address outputs 22 of the device .

The device works as follows.

Consider the principle of operation using time diagrams (Fig. 2), where a case of processing three analog signals U, and, is shown.

15

20

and, (the device contains, for example, 3 channels).

When the front edge of a pulse arrives at a moment t from the direct output of the master oscillator 7 pulses to one of the inputs of the multi-input element I 13, the other inputs of which have levels 1, a single level will be set at its output opening the key 3 and as a result The process of charging the capacitor 5 begins. At the time t, the voltage at the output of the operational amplifier 6 reaches the value of the smallest of all channel voltages (in Fig. 2, this is the voltage of the first channel t / l) and the comparator 10 of the first channel is triggered,The output of which appears is level 1. As a result, the front of the pulse 11 is fed to the input of the first channel generator 11, which triggers the generator, which produces a negative pulse with a duration equal to the required storage time of the selected discrete value, during which it is produced processing, such as analog-digital conversion or other operations. Other shapers 11 and 12 work similarly. From the output of the former 11 channel former, a negative pulse is applied to one of the inputs of the multi-input element I 13, 35, as a result of which a negative pulse appears at its output, the shaking of switch 3 and the stopping charge of the capacitor 5 for the duration of this pulse. In addition, from the output of the same shaper 11 im-

25

thirty

A pulse is applied to one of the inputs of the first element of AND block 15, and at its first output a pulse of the same duration appears.

At the moment of time. t (at the end of the pulse generated by shaper 1I of the first channel), at the output of element 13, a single level is again established, which opens the key 3 and continues the process of charging the capacitor 5 linearly through a resistor 1 from the voltage source -K (not shown).

At the moment of time

when and

5 - H, - jt, v

operational amplifier 6 reaches the value of the smallest of the remaining channel voltages (in FIG. 2, voltage u), the comparator is triggered

10 of the second channel, at the forward output of which the leading edge of the pulse appears, triggering the driver

11th channel, which produces a negative pulse. This pulse through the element And 13 (b,) is fed to the control input key 3

and closes it before it ends, i.e. before time 1, as a result of which the charge of the capacitor 5 stops, which indicates the end of the storage process of the discrete value of the second signal. The pulse shaper 1I of the second channel through the second element And the block 15 is also fed to the control output of the second channel. After its termination (at the moment of time), the process of charging the capacitor 5 begins again, which will continue until time t, when the voltage at the output of the operational amplifier 6 reaches the value of the last of the remaining channel voltages (in the plot of Fig. 2, the voltage U ) and as a result, a third channel comparator 10 is triggered, at the forward output of which is the leading front of the igotulse, which triggers the third channel generator 11, which produces a negative pulse. This impulse through the element I 13 enters the control input of the key 3 and closes it until its termination, i.e.

to the point in time

as a result

which terminates the charge of the capacitor, which indicates the end of the process of storing the discrete value of the last of the voltages. Impulse forming device 11 third ka-i

Nala through the element And block 15 is also fed to the address output of the third channel. After it ends (in my

time ment tg; the process of charging the capacitor 5 will begin again, which will continue until time point t, g, when the voltage at the output of the operational amplifier 6 reaches

the maximum positive value of the range of variation of the input signals and arriving at the non-inverted input of the comparator 8 (K +), at the output of which the level of

It is through the element AND 13 is the closing key 3.

The charge phase of the capacitor 5 begins at time t, |, when the leading edge of the pulse arrives from

the rotating output of the generator 7 to one of the inputs of the element And 14 (U.

 M 2

on the other inputs of which levels 1 are located. Pa its output will establish a single level opening key 4, as a result of which the capacitor 5 is discharged linearly through a resistor 2 from a voltage source + E (not shown). At time t, the voltage at the output of the operational amplifier 6 reaches the value of the greatest of all channel voltages (in Fig. 2, the voltage of the third channel U) and the comparator 10 of the third channel is triggered, at the inverse output of which the leading edge appears, - impulse that triggers the third channel driver 12, which produces a negative pulse. This impulse goes through the element I 14 (U ",) to the control of the 1st input of the key 4 and closes it until its end, i.e. until time t, as a result of which the process of discharge of capacitor 5 is reduced, which indicates the end of storage of the discrete value of the selected channel voltage. The impulse of the former 12 generator of the third channel through the element And block 15 also enters the output 22 of the third channel. After its termination (at time t, 2), the process of discharging capacitor 5 will begin again, which will continue until the time t when the voltage at the output of operational amplifier 6 reaches the highest of the remaining cassal voltages (in Fig. 2). b) and the comparator 10 of the second channel is triggered, at the inverse output of which appears the leading edge of the pulse, which starts the driver 12 of the second channel, which produces a negative pulse. This impulse through the element 14 (CC,) enters the control input of the key 4 and closes it until its end, i.e. until time t, as a result of which the process of discharge of capacitor 5 stops, which indicates the end of storage of the discrete value of the second channel voltage. The impulse shaper 12 of the second channel through the element And block 15 is also fed to the output 22 of the second channel. After its termination (at time t, 4), the process of discharge of capacitor 5 begins again, which will continue until time t, when the voltage at the output of operational amplifier 6 reaches the value of the last of the remaining channel voltages (Fig. 2). U,) and the comparator 10 of the first channel is triggered, at the inverse output of which appears the leading edge of the pulse triggering the former 12 of the first channel, which produces a negative pulse. This pulse through the element And 14 (and ") goes to the control input of the key 4 and closes it until its end, t, e, until the time point, as a result of which the discharge of the capacitor 5 stops, which indicates the end of the storage of the discrete value first channel voltage. The pulse shaper 12 of the first channel through the element And block 15 is also fed to the output 22 of the first channel. After its termination (at time t,), the process of discharging capacitor 5 will begin again, which will continue until time t,.., When the voltage at the output of operational amplifier 6 reaches the maximum negative value of the range of input signals U, to the inverting input of the comparator 9 (k -), at the output of which the level O is set, through the AND element 14 the closing key 4.

From the moment when the leading edge of a pulse arrives from the direct output of the master pulse generator 7 to one of the inputs of the element 13816036

I- and 13 (,) again begins the phase of the charge of the capacitor 5 and all the processes are repeated as described above.

Analyzing the operation and time diagram of operation (FIG. 2) for several sampling steps, it can be concluded that the proposed device provides for sampling and storing discrete values of channel voltages within a single sampling step sequentially not by channel number, but sequentially by rank.

Jc i by the values of channel voltages, starting with the lowest of all and ending with the highest - during the phase of charging of the capacitor 5, starting with the highest of all and ending

The 2Q is the smallest during the discharge phase of the capacitor 5. In FIG. 2, the following order of sampling and storage of voltages is observed: 1 sampling step (charge phase) —and, and, .and ,; 2 step (fa25 per discharge) - U ,, U ,, U, etc.

The device simultaneously performs the functions of multichannel switching (switching with adaptation and to the levels of channel voltages) and the functions of an analog storage device, i.e., sampling and storage of discrete values.

The number of channels can be arbitrary, however, it is necessary to take into account that the maximum number of channels is determined by the maximum rate of change of channel voltages (i.e., their dynamics), sampling error, sampling and storage, as well as

. the relative position of the channel voltage, as a function of time, one relative to another. The minimum pulse duration of the generator 7 is determined by the charge rate and the discharge rate of the capacitor 5, and also 35

45

the same storage time of discrete values of the signals and is calculated by the formulas:

1 + -Gzm.ks + P. t

L1}

BI

50

.

+ i

T-P V

 rm about cs xp

l and ix

 -g, - + P. t,

55-

where T + is the duration of the positive pulse of the generator 7;

the relative position of the channel voltage, as a function of time, one relative to another. The minimum pulse duration of the generator 7 is determined by the charge rate and the discharge rate of the capacitor 5, as well as

the same storage time of discrete values of the signals and is calculated by the formulas:

1 + -Gzm.ks + P. t

L1}

BI

.

+ i

T-P V

 rm about cs xp

l and ix

 -g, - + P. t,

55-

where T + is the duration of the positive pulse of the generator 7;

 3 max

7138;

t - is the duration of the negative pulse of the generator 7;

U 5 - range of input signals;

- charge time of the capacitor 5 from the maximum negative limit of the range of change of the input 10 signals to the maximum positive;

time of discharge from the maximum positive limit of the range of variation of the input signals to the maximum negative;

-

p maicc

,five

Uj is the charge rate of the capacitor 5;

Up is the discharge rate of the capacitor 5;

n is the number of signals; O - storage time

discrete values of the signals (assumed equal for all signals). It should be noted that the input signals must be limited in terms of the growth rate, since if this requirement is not met, the signal may be re-sampled on the same channel, which entails undercharging the capacitor to the range limit due to additional sampling and storage of this signal, which can lead to the danger of non-sampling of signals, found with their near the border of the range. But this danger can be eliminated by providing some margin for the duration of the pulses of the master oscillator 7. The use of comparators 8.9 (K +, K-) makes it possible to eliminate the floating of the input signal range with possible simultaneous sampling (Fig. 21 i4b ;; j) of several sig This can lead to the recharging (re-charging) of the capacitor 5 relative to the range boundary.

The increase in speed is achieved by using the discharge phase of the capacitor as the working phase. Therefore, the duration of the step disk

38

The test results are reduced by the time required to discharge the capacitor in the prototype device from the maximum positive limit E1 of the measurement range} of the input signals to the maximum negative one.

Claims (1)

Invention Formula a low voltage device with a device containing a cumulative element on a capacitor, the plates of which are connected to the input and output of the operational amplifier, respectively, the first and BTopoii passive elements on resistors, the first terminals of which are the connection; with information inputs of the first and second keys of the corresponding The outputs of the switches are connected to the input of the operational amplifier, the output of which is the information code of the device, the second terminals of the resistors are connected respectively to tires of positive and negative voltage of the device, clock generator, main components, the first inputs of which are informational inputs of the device pulse shapers, the first element And, differing from the fact that, in order to increase the speed of the device, it is added to it: 1 s comparators, the second AND and the AND block, the outputs of which are the address outputs of the device, the inputs of the AND block of the menus And are connected to the outputs of the pulse former and the first inputs MJi of the first and second elements And, the second inputs of which are connected to the outputs of the generator of clock pulses, the third inputs of the first and second elements I are connected to the outputs of the additional comparators, the first inputs of the additional and second inputs of the main comparators are connected to the output of the operational amplifier, the second inputs of the additional comparators are The inputs of the device reference voltages, OUTPUT 111 of the first and second elements I are connected to the control inputs of the first and second keys, respectively. and, K1 Ug Uf (z Vpi . Up. L V ,, V,  / (and, CHN1 Uh Mi u, V ,, z