SU1363518A2 - Apparatus for autocorrelation reception of first-order phase-difference modulatedsignals - Google Patents

Abstract

The invention relates to a communication technique and provides enhanced functionality by receiving signals with phase difference modulation of higher order. The device contains a controlled phase shifter 1, multipliers 2 and 3, delay lines 4 and 10, phase shifter 5 at 7f / 2, integrators 6 and 7, threshold unit 8, synchronization unit 9, inverter 11, electronic switch 12, generation unit 13 control signals. Decisive blocks 14 are newly introduced, each of which contains a memory block 15 and an adder 16 modulo two. 1 il.

Description

The invention relates to communication technology and can be used in discrete information transmission systems.

The purpose of the invention is to extend the functionality by receiving signals with phase difference modulation of higher order.

The drawing shows a structural electrical circuit of the proposed device.

The autocorrection signal reception device with phase difference modulation of the first order contains a controlled phase shifter 1, the first 2 and second 3 multipliers, the first delay line 4, the phase shifter 5 on, the first 6 and the second 7 integrators, the threshold unit 8, the synchronization unit 9, the second a delay line 10, an inverter 11, an electronic switch 12, a control signal generating unit 13 and decision blocks 14.

The decision block contains a memory block 15 and an adder 16 modulo two.

The device works as follows.

When the device arrives at the input of the signals from FRM-K (K 2) in the first quadrature branch using the multiplier 2, and the integrator 6, the scalar product of two adjacent signal bounds -Xj (t) Hx -, (t) is calculated proportional to the cosine of the first phase difference of these signals, i.e.

ah

1) x,. / T)

"OS (1.)

h

ah

cos (l 1 +

where a is the signal amplitude at

device input; - random non-informative phase value, caused by frequency instability and (or) duration of the first line delay and delay. At the same time, in the second quadrature branch, using multiplier 3 and integrator 7, the scalar product of the signals is calculated and

Xy, .i (t), where the bar denotes the Hilbert transform performed by the phase rotator 5 on / 2. At the same time, the integration is performed in the O-T / 2 time, which provides for an increase in the noise immunity of the reception in case of rapid changes in the signal frequency.

t ft

ah

1, j x (t) x „. (t) a

sin (1, + 2)

If the frequency and duration of the pitch of line 4 are constant and equal to their nominal f values, responsibly, then O and

and od with

 Max

and Ij 0.

If the frequency and / or duration of the delay of the first line 4 of the delay is variable with time, then and are non-zero and the output of the electronic key 12 forms a voltage proportional to the sine of the non-informational change of the signal phase:

 g

1 sign 1. .

Further, this voltage is digitized in block 13 of generation of control signals and

arrives at the second (control) input of the controlled phase shifter 1, with which the phase ratios of the signals multiplied in the multiplier 2 and 3 are set so that

To ensure the maximum value of the voltage at the input of the threshold unit 8. From the output of the threshold unit 8, which performs the function of determining the sign of the signal at its input, are positive and negative.

impulses (according to sign

the cosine of the first phase difference of the adjacent signal sprinkling from the FRM-K) is fed to the input of the memory block 15 and the second 3113

There is a modulo two of the first of the K-1 identical decision blocks 14. At the same time, at the output of the sump 16 modulo two pulses are generated, the polarity of which corresponds to the sign of the second phase difference of the signal with PRM-K. If, for example, i. the information is embedded in the second phase differences of three neighboring signal streaks, i.e.

l 1., p - 2k +

O - S

+ cf

n-l

that decision sign

may be accepted by. cosine.

sign I sign cos 4 I / sign cos

(e cf - 4JI,. C)) sign (cos L n × X “COS l c + sin 4 1 sin l 4)

This happens only when the effect of frequency instability and delay time of delay line 4 is compensated, which is achieved by having a feedback branch by solving and adjusting the phase relations of multiplied signals in the first processing branch using a controlled phase rotator 1. Follower steady-state values of the sines of the first phase differences are zero and the equality

sign I sign (cos l V) sign y

x (cOS4j lCCOb)

which corresponds to the operation of adding modulo two values of the cosines of the first phase differences of the neighboring premises of the signal with PRM-K, i.e .:,

Editor T. Lazorenko

Compiled 0. Heller,

Tehred I.Popovich Proofreader I.Musk

Order 6384/56. Circulation 636 Subscription

VNIIPI USSR State Committee

for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab. 4/5

Production and printing company, Uzhgorod, st. Project, 4

sign I sign (cos / J, cos l h) TTloa 2

Thus, at the output of the adder 16 modulo two of the first decision block 14, the polarity of the signal reflects the cosine sign of the second phase difference, which corresponds to demodulation of signals with a second-order FRM. Similarly, at the output of the adder t6 modulo two of the second decision block 14, calculation of the sign of the cosine of the third phase difference of four adjacent signal packages:

sign I sign (cos, gi),

 tnodt

Those. etc.

demodulation of signals from FRM-3 and

Claims (1)

The formula will be chosen. Device for autocorrection signal reception with phase difference. first-order modulation by author. St. No. 1256237, characterized in that, in order to expand the functionality of nji TeM receiving signals with phase difference modulation of higher orders, serially connected decision blocks are introduced, the clock inputs of which are connected to the first synchronization block Bbixojjy, the signal input of the first decision block is connected to the output of the threshold block, the output of the last decision block is the output of the device, with each decision block containing a modulo two li block of memory whose output is connected to the first input sum ora modulo two, the second input of which is connected to the first input unit and the memory signal input is decisive block synchronizing input which is the second input of the memory unit, and the output of the adder modulo two is output deciding unit.