SU1363231A1 - Failure-simulating device - Google Patents

Abstract

The invention relates to modeling devices and can be used in the design of electronic, technical, ergatic systems for evaluating performance indicators and developing proposals for improving the reliability of systems. The purpose of the invention is to increase the reliability of the simulation in the absence of information about the operating conditions of the object under study. The goal is achieved by introducing into the device of the memory block weights, a clock generator, a simulation time counter, a number of realizations counter, a frequency multiplier and a result processing unit including a one-shot, element I, a group of pulse counters, a divider group and a group of memory registers. The device makes it possible to simulate in the design process failures of complex systems in the absence or limited volume of statistical data on the operating conditions of the systems. 5 il. (L 00 05 WITH N5 WITH

Description

The invention relates to modeling devices and can be used in the design of electronic, technical, ergatic systems for assessing performance indicators and developing proposals to improve the reliability of systems.

The purpose of the invention is to increase the reliability of modeling.

Figure 1 shows a diagram of the proposed device; 2 is a diagram of a signal distribution unit; FIG. 3 is a diagram of a processing unit; Fig. 4 is a diagram of a weight storage unit; FIG. 3 is a timing diagram explaining the operation of the device.

The device for simulating failure mode contains a control block 1, a generic value threshold of 20 and a matching of 2 random signals, a comparison block-3, a weight memory block 4, a signal distribution block 5, a result processing block 6, a recording block 7, a generator clock pulses, block of 9 multiplication of clock, counter 10 of simulation time, counter 11 of the number of realizations.

The switch contains the register 12 shift, the multiplexer 13, the first decoder 14, the counter 15 pulses, the second decoder 16, the element OR 17, the group of elements And 18.

The result processing unit contains an element 19, a one-shot 20, counters 21, dividers 22 of memory registers 23.

Weight memory unit 4 contains AND 24 elements and memory nodes 25.

The basis of the operation of the device is the determination of the membership function of failures, which takes a value from the interval Г0.1 and characterizes the degree of belonging of each element to the fuzzy subset. The value of the membership function of failures for each element of the odd subset, i.e. for each specific value of the threshold level, quantitatively characterizes the objective possibility of system failure when the parameter crosses this level.

The results of determining the moment of the system failure will in this case also be fuzzy. They are represented as the expectation of the membership function of the moment of failure to the considered operating interval.

(analogous to the mathematical expectation of the distribution density of the failure time obtained by representing the values of the threshold levels using the mathematical apparatus of the theory of random processes). The values of the mathematical expectation of the membership function quantify

the possibility of system failure at any time interval operation.

The device works as follows.

Before starting work, the results of quantization of a curve characterizing the degree to which the parameter values belong to an odd subset of threshold levels are then used to simulate

25

thirty

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their weights from the interval of 0.1. Figure 5 shows an example with quantization on levels 0; 0.25; 0.5; 0.75; I. The values of the thresholds formed by the abscissas of the points of intersection of the quantization levels with the curve are attributed to weights equal to the value of the given quantization levels. Using the control unit (which is, for example, a dial pad, the dialing is carried out using buttons or switches), threshold levels are set in comparison block 3 and pulses corresponding to the weight of each threshold level are recorded in the memory 25 of block 4. For eliminating uncertainty, zero weight corresponds to the minimum number of pulses equal to the selected number of realizations of the parameter. The same number of implementations is recorded in the processing unit 6 of the results and sets the maximum capacity of the counter 11 to the number of realizations. The control unit also sets the desired characteristics of a random process for changing a parameter modeled by the random signal generator 2. The entire operation interval, on which it models, the process of changing parameters, is divided into a number of subintervals (Fig. 5) for the subsequent calculation of the total value of weights of threshold levels that the parameter crosses in the groove of the subinterval, and obtain the resulting statistical characteristic. Codes corresponding to the subinterval boundary values are recorded in block 5.

31363231

The device starts the process model

with the appearance of a signal. Triggering at the output of control unit 1. This signal triggers the 8 clock pulse generator and 2 random signals generator. The pulses from the output of the generator 8 are counted by a time counter 10, its content determines the time corresponding to the operation time from the beginning of the simulation of the next implementation. The frequency of the oscillator 8 clock pulses is chosen so that the time is calculated in units corresponding to the methods accepted to account for the operating time of the simulated object. (seconds, minutes, hours, etc.) The generator 2 of random signals starts outputting the analog voltage corresponding to the implementation of the simulated parameter. The presetting of the random process characteristics for the generator consists in the installation from block 1 of the control of the value of the correlation coefficient between the initial value and the rate of change of the parameter. The signal from the output of generator 2 is fed to block 3 of the comparison. In block 3, a comparison is made of the value of the parameter implementation and pre-enumerated threshold levels. When the next threshold level is crossed by the parameter, a rectangular pulse appears at the corresponding output of block 3.

The impulse from the output of the comparison unit 3 allows the reading of a number proportional to the weight of the crossed threshold level from the memory block 4 to the block 5. When a pulse appears at the input of block 4, it passes to the input of the corresponding element 24, allowing pulses to pass through it from block 9 multiplying the input of the node 25 to control the read. The multiplication unit 9 performs the functions of a frequency multiplier, therefore reading the information about the weights of the threshold levels recorded in the nodes 25 occurs at high speed. After each read, the contents of the corresponding register are restored. The duration of the pulses generated in block 3 is chosen from the sufficiency condition for carrying out the described reading operation.

The sequence of pulses, the number of which is proportional to the weight of the next crossed level,

comes from the output of block 4 to the input of the block 5 distribution of signals-. The number of its information inputs is equal to the number of threshold levels, the number of outputs is the number of subintervals, into which the considered interval of operation of the simulated object is divided. A sequence of pulses arriving at the input of block 5 passes to its output corresponding to the subinterval in which the considered crossing of the threshold level occurred.

Unit 5 operates as follows (figure 2). First decoder 14

connected in parallel with the counter 10 time. High potential on any. from the outputs of the decoder 14 and, accordingly, on any of the first inputs of the multiplexer 13, only

at a certain content of the counter 10. The output of the multiplexer 13 is connected

about

From the inputs whose number is fed to its second input from the shift register 12. In the shift register, codes are preliminarily written down one after another, equal to the numbers of the outputs of the decoder 14, the high potential on which appears when

the contents of the counter LO is T

one

T / 2, ..., T, respectively (hereinafter, the indicated outputs of the decoder will be called 14 first, ... n-th). For each code in register 12, the same number of bits is allocated. The high bits of register 12, the number of which is equal to the size of one code, are connected to the second input of the multiplexer 13. At the initial moment, they recorded the code of the first output of the decoder 14.

The contents of counter 15 are equal O, high potential is present at the zero output of the second decoder 16, permitting the passage of sequences of pulses carrying information about the threshold levels crossing the parameter through the first of the elements And 18 to the output of block 5 corresponding to the first subinterval of the modeled operation interval. On the other outputs

decoder 16 - low potentials that prohibit the passage of information through other elements I. As soon as the contents of counter 10 become equal to T, the high potential from the corresponding output of the decoder 14 passes through multiplexer 13 to the input of counter 15. The transition 0-1 is fixed by the counter, and the high potential is now is present at the first output of the decoder 16, allowing the passage of sequences of pulses through the second of the elements And 18 to the output of block 5, which corresponds to the second interval of operation. A negative voltage drop of 1–0, which occurs at the output of multiplexer 13 when the content of counter 10 is changed by one (and increasing the number of output of high potential potential generator 14, goes to the first input of the shift register 12, causing a shift by the number of bits, equal to the digit of one number. The code displaced from the higher bits is written again to the lower minor bits. Now the second (address) input of the multiplexer 13 contains the code of the second output of the decoder 14, Described negative first the output multiplexer 13 output is not detected by the counter 15, and its state does not change until the content of the counter 10 becomes equal to T. The cycle of the switch is repeated.

The sequential shift of the codes in register 12 causes that during the simulation of a parameter change in the interval T, T., the output of the register contains the code of the first output of the decoder 12, and this part of the switch is ready for operation with the following implementation. As soon as the contents of the time counter 10 become equal to Tj, the overflow pulse from its output through the third input of the switch nulls the counter 15. Block 5 thus transitions to its original state and is ready for operation with a new implementation.

The composition of the elements of block 5 and the relationship between them make it possible to choose different values of the boundaries T ,, Tj, ..., when modeling each particular parameter, in the interests of a more accurate study of the resulting statistical characteristics in those periods of operation when the failure of the modeled object is most likely 7 ten

An overflow pulse from the output of the time counter 10 also passes.

0

five

five

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five

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five

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five

on the fourth input of the generator 2 random signals, transfer it to the mode of modeling a new implementation. The same impulse arrives at the counter 11 of the number of implementations. Counter 10 itself is zeroed. The device starts a new similar simulation cycle.

When the contents of the counter 11 of the number of implementations becomes equal to the set, i.e. when the capacity of the counter pre-installed from the control panel 1 is overflowed, the overflow pulse from its output goes to the input of the generator 2, stopping the modeling process, to the input of the generator 8, stopping the output of clock pulses, and to the fourth input of the processing unit 6, giving the command to process . The results of the processing performed by pulses from the output of block 9 are recorded in block 7.

Unit 6 processing of results operates as follows.

During the simulation, the pulses from the output of the switch 5 pass to one of the other meters 21, depending on which of the simulated subintervals of operation the level intersects. After completing the simulation in each of. counters 21 recorded the number corresponding to the total weight of the crossed levels during a specific subinterval. Overflow pulse. from the output of the counter 11, the number of implementations triggers the one-shot 20. A rectangular pulse from the output of the one-shot (the pulse width is chosen sufficient for processing) permits the passage of clock pulses from the output of block 9 multiplying by counters 21. These pulses control the reading of information from counters by dividers 22. Previously, the assigned number of implementations of the modeling process is written to the dividers through other inputs from the control unit. At the output of the dividers in Vits and registers in the registers a number equal to the quotient from dividing the contents of the drives by the number of implementations. From the output of registers 23, the processing results corresponding to the statistical estimates of the mathematical expectation of the membership function of the moment of failure are received at block 7 of registration. Here, for binding the simulation results to the operation time, the subinterval boundary values are supplied. Processing results can be recorded, for example, in the form shown in Fig. 5. The result of the division performed in block 6 is greater than the true value of the degree of membership by the number of times the number of pulses recorded in the registers of block 4 is greater than the true value of the weights of the threshold levels. It is more convenient to choose this coefficient of proportionality equal to Yu, where m is assigned depending on the required accuracy. Then, when m 1 in the registration process, the separator sign between the integer and fractional parts of the division result must be moved one digit to the left, and the value of the membership function must be calculated to the first digit; at m 2, a separator sign is needed for the re2Q one-shot, the input of which is connected to the overflow output of the counter. the number of implementations, the stopping input of the random signal generator and the stopping input of the clock generator

carry two bits to the left, and the calculations to be performed with an accuracy of up to 25 pulses, the block of distribution of the signal mark, etc., contains the shift register, in a multi-way manner, the proposed device, the first and second decoders, allows you to simulate a pulse trainer, the OR element and

a group of elements And whose outputs 30 are connected respectively to the counting inputs of the pulse counters of the group of the processing unit, and in the signal distribution unit the outputs of the first decoder are connected to the design process failures of complex systems in the absence or limited amount of statistical data on the operating conditions of the systems.

Claims (1)

Invention Formula A device for simulating failures, comprising a random signal generator, a comparison unit, a signal distribution unit, and a control unit made in the form of a number sensor. 35 Responsibly with the information inputs of the multiplexer, the control inputs of which are connected respectively with the group of high-order bits of the shift register of the signal distribution unit, the input field and the source constant 40, the output of the multiplexer is connected to a voltage connected to the button. The input of the shift register and the counting start, the outputs of the number sensor are connected respectively to the inputs of the input field, the output of the Start button is connected to the start input of the random signal generator, the outputs of the input floor are connected respectively to the installation input of the random signal generator and the information inputs of the first group of the comparison unit, characterized by that, in order to increase the reliability of the simulation in the absence of information about the operating conditions of the object under study, it additionally contains a scale memory block x ratios, a clock pulse generator, a time counter simulation, the number of implementation of the counter, multiplier chas45 50 55 the input of the pulse counter of the signal distribution unit, the bit outputs of which are connected respectively to the inputs of the second decoder, the outputs of which are connected respectively to the first inputs of elements AND of the group of the signal distribution unit, the second inputs of which are connected to the output of the element OR, the inputs of which are connected respectively to the outputs of the memory block These weights, the address inputs of which are connected respectively to the outputs of the comparison unit, the information input of which is connected to the output of the case generator A signal whose restart input is connected to the overflow output of the simulation time counter, the counting unit and the processing unit consisting of a one-shot, element I, a group of pulse counters, a group of dividers and a group of memory registers, the bit inputs of which are connected respectively to the outputs of the dividers of the group and the bit outputs of the memory registers of the group are the outputs of the device, the first information inputs of the group divisors are combined and connected to the corresponding output of the keypad And second data inputs of dividers 5 groups are connected respectively to the bit inputs of the group counters, the read inputs of which are combined and connected to the output of the element I, the first input of which is connected to the output Q one-shot whose input is connected to the counter overflow output. the number of implementations, the stopping input of the random signal generator and the stopping input of the clock generator 5 pulses, the signal distribution unit contains a shift register, multi 35 Responsibly with the information inputs of the multiplexer, the control inputs of which are connected respectively to the group of high-order bits of the shift register of the signal distribution unit, 40 the output of the multiplexer is connected to the shift input of the shift register and the count5 0 five the input of the pulse counter of the signal distribution unit, the bit outputs of which are connected respectively to the inputs of the second decoder, the outputs of which are connected respectively to the first inputs of elements AND of the group of the signal distribution unit, the second inputs of which are connected to the output of the element OR, the inputs of which are connected respectively to the outputs of the memory block These weights, the address inputs of which are connected respectively to the outputs of the comparison unit, the information input of which is connected to the output of the case generator The signal whose restart input is connected to the overflow output of the simulation time counter, the counting input of the number of realizations and the zeroing input of the pulse counter of the signal distribution unit, the inputs of the first decoder of which are connected to the bit outputs of the simulation time counter, the counting input of which is connected to the output of the clock pulse generator and the input of the frequency multiplier, the output of which is connected to the second input of the element AND the block, processing the results and the information readout input of the memory block of weight coefficients, the output of the Start button of the control unit is connected to the start input of the clock pulse generator, and the information inputs of the weight coefficient memory block, the bit inputs of the shift register of the switch and the counter of the number of realizations are connected to the corresponding to outputs of a type-setting floor of the control unit. 41 g, f ifcj Par.2 L fK Gz Editor A.Makovska Compiled by V.Fukalov Tehred M.DIDYKKorrektor A.T. sko, Order 6364/42 Circulation 671 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4