SU1352369A1 - Device for measuring parameters of rotor rotation in transient conditions - Google Patents

Abstract

This invention relates to a measurement technique. The purpose of the invention is to increase ToqisocTH izreni. Register 51 stores the smaller value of the period of the measured frequency. After filling the counter 47, a pulse arrives at the trigger 46 and it is set to the zero state, locking the element 48, and the clock frequency from the split 7 does not pass to the counter 47 Minimum number converted in calculator 53 of the calculation and display 56 The rotor rotates, highlighted as the maximum rotor speed. When operating in the memory mode, the 1-tu. Tracks arrive at both inputs of the HTui 24 element simultaneously. 1 il. G /) ii i K5 SA5 ssp., Cig s-

Description

The invention relates to a measurement technique and can be used to automatically measure the rotor speed, time and speed of run and memorize maximum deviations of the rotor speed in transient conditions, such as steam rotors, gas turbines and hydraulic turbines.

The aim of the invention is to increase the measurement accuracy.

The drawing shows a diagram of the device.

Frequency sensor 1 turn is rigidly connected to the rotor, the rotational speed of which is controlled and the output is connected to the former 2 standardized pulses 5 which the output is simultaneously connected to the input of unit 3 of the start of deceleration and the input of the unit 4 speed measurement unit 5.

The RSwartz generator 6 of the reference clock of the 25 block is connected to the second input of the dot connected via a divider 7 from the 2I-NO 14 block of block 4. In addition, the period count 8, the control block 9, the first gate trigger 33 of the block 15

is connected via an inverter 34 to the second output of block 4. Block 15 forms

thirty

laziness and block IO of controlling the beginning and end of the comparison of block 1 for allocating a minimum,

pause long duration when run out (negative acceleration) of the rotor

The automatic speed measurement unit 5 consists of five units. The main block 4 sets clock signals 5 consisting of a counter 12, to the input of which, through the first input of the ZI-NO element 13, signals from the frequency sensor I through the driver 2 and the first input of the switch 2I-HE 14; as well as from the block of formation of long pauses 15 through the second input of the key 2IHE 14, through the input of the ZI-NO 13 element from the memory management unit 9 of the memory unit I6 and also from the device 17 Initial state of the unit 18. Third output unit 4 connected to the second input of the counter 19 of the block 8 through the inverter 20 and. Differentiator 21. The second output unit 4 is connected to the second input of the control unit 22 of the Cell number counter via element 2И-НЕ 23 and to the third input of the unit 15f and also the OR 24 element of the display unit 25, the first output unit 4 is connected to the second input of the random access memory (RAM) 26 block / 16 memory. Through differentiator 27. Block 4 generates signals whose duration is inversely proportional to the speed (frequency) of the rotor rotation.

The block 3 for fixing the moment of the start of braking consists of a frequency-voltage converter 28, which is supplemented by a threshold device 29 and a driver 30 of control signals. Signals from the first output of block 3

served to the second input of the block 15 for the formation of long pauses. From the second output of block 3. The signal is fed to the first input of block 22 of control of the counter of the number of cells of the memory block via element 2I-NOT 23. Block 3 generates signals depending on the sign of acceleration.

Block 15 forming long pauses consists of a counter 31

cycles, to the input of which is connected through the key 2I-NOT 32 crystal oscillator 6, the second output of the block 3, the second output of the trigger 33 and the output of the element 17 The initial state of the block 18, and you

0

five

0

five

long pause when running out (negative acceleration) of the rotor.

The period counting unit O consists of a counter 19 and a key 2I-NO 35, to the first input, which is fed a signal from

block 4 task clock signals on

I

the second input is a signal from quartz

generator 6 through block 7. Block 8 output is connected to RAM 26 of memory 16 block. Block 8 generates a Binary code signal that is inversely proportional to the rotation frequency f of the rotor.

The memory block 16 consists of four blocks. The main unit is a RAM block 36, the inputs of which are connected to blocks 4 and 8 of the automatic speed measurement block 5 and the cell number counting block 37, the first output of which is also connected to the cell number indicator 38 of block 25 indication-. The output of the block 36 is connected to the second outputs of the comparison (calculation) blocks 39 and 40 of the minimum register of the minimum division block 11. The input of the cell number counting unit 37 is connected to the second output of the number control unit 22. cells, which consists of and .. from the circuit 2I-NOT 23, RS-flip-flop 41, circuit ZINE 42. To the input of block 22 is given sig3135 2369

rolls from blocks 3 and 4 of the automatic block 56 for calculating and indicating speed velocity measurements. Rotor rotation unit 22. Display unit 55

generates signals to switch the cell number with its input connected to

checker. in the second output of block 37

Memory management unit 9 consists of cells of memory block 16, and block 56 of the memory reset trigger 43, the OR-24 element is transferred to the third output of which through the circuit 2I-NE 44 of the block 37 and the third output The control button and the trick 4 are turned on. The display unit provides the setting unit 18 to the initial state, resetting the number of periods to a value of konii, and a second rotation is connected to the second input, reading these coefficients 45 to the second output of the blocks and marking them. . ka 37 bills numbers of cells, as well as from the device, in addition, contains

trigger 46, the first input of which is inverter 57, element 2I-HE 58, differential-connected to the second output of the 47 g counter, ferentiator 59, element 2I-NOT 60, cells of the block 37, and second input 2I 61, differentiator 62 With unit 18 of installation into the original connection- The device operates as follows. Inverse output through elezraz.

mant 48 trigger 46 is connected to the unit. At the moment of power switching on, impact 22, and the second output is connected to the second controller. The initial state is input to the control unit 10 and the start of the element 17, triggers 33, unit 15 and 43

the end of the comparison of the If block in the block 9 block, as well as the counters 19 of block 8

neither the minimum. and the 47 blocks 37 are set, at the zero allocation block 11, the state of the state. The counter 12 of the block 4 is installed out of four blocks: the block 39 is compared to the binary state.

non (subtraction), block 40 of the register code of which corresponds to 9, with.

minimum, recording control unit 49 after the signal is removed Initial

in the register and the control unit 10 start-state pulses on the counter 19

The scraper and the end of the comparison of block 8 from the divider 7 do not pass; by element 50 of comparison of block 39, the pulse from the second input measured by it is not received from the output of frequency f and will not translate counter 12 of RAM 26 of block 36, by the third input of - unit 4 to the state O. With this mono-inverse output of the register-minimum 51 moment, the first cycle of the measurement block 40 begins, and the output - with the first input, For eight periods, which is element 52 of the block 49. The register-mini- rye counts the counter 12 of block 4, the mum 51 of block 40 with the first input of the connection meter 19 of block 8 is filled with one hundred It is connected with the output of control unit 49 by blocking pulses from the delimit into the register, the second input is the stele 7.

the output of the RAM 26, the first output — With the completion of filling through the third input of the block 39 and the second step-up of the elements 57, 27 of the block 4 into the RAM by a stroke — with the input of the circuit 53 the calculator of the block 36 receives the recording signal and the speed indication of the block 25 the indie information contained in the counter (Kacija.ke 19, block 8, is transferred to the first recording control unit 49 in RAM 26 and simultaneously to the register, consists of logic elements 51. At the end of the transfer of int 2I -NE 52 and ZI-NOT 54; Blocking output while maintaining a positive 49 is connected to the first input of the th acceleration, a pulse passes on the hyste-minimum 51. The inputs of the block 49 are the counter 47 of the block 37 and are connected to the output of the block 10 by a control-next RAM cell for writing. After the start and the end of the comparison, the reset signal goes to the counter 19 by the block 46. In through the elements 59, 20, 21

Block 1 1 provides an alternate block 4, which sets the counting — comparing the values of the number of periods of the vchik 19 to the zero state. The cycle of counted intervals, information and records is repeated. In the case of which data is stored in RAM, select, df.

its speedbeat (-J-- - (J) counts the minimum value and transmits, at

its calculator tor. block 47 of block 37 retains its display unit 25 consists of a block, and at the end of the next

ka 55 indication of the number of the cell and block-cycle new information from the counter 19

recorded again in the first cell of RAM and register 51,

Upon the occurrence of negative acceleration, element 30 of block 3 receives a signal l, which permits the passage of a pulse from differentiator 59 to the trigger 33 of block 15. This pulse sets the trigger 33 to one state. at the same time, element 4 of block 4 receives a signal O, which prohibits the passage of pulses of the measured frequency, and element 32 of block 15 receives a signal l, which permits counting of pulses from the divider 7 by the counter 31. Thus, a long pause i 30 s is formed. fill counter 31.

At the end of the counting, the counter 31 of the block 15 outputs a pulse to the trigger 33 and sets it to the state O, while the block 4 is put into operation and performs a cycle for measuring the duration of the period recorded in the memory, after which a pause is again formed T T 30 s . This mode of operation is performed before filling the counter 47 of the block 37. After filling it, a signal is generated from the counter 47 to set the trigger 43 to the state 1, and the write to the RAM is stopped due to the incoming signal O on the element 13 of the block 4 and stopping the operation of this block.

At the same time, the inverse output of the flip-flop 43 of the block 9-appears signal l and the element 44 permits the passage of the signal from the divider 7 to the counter 4 of the block 37 through the elements 42. and 60 of the block 22.

In this case, the adder 50 of block 39 compares the contents of register 51 with the corresponding cell of RAM 26 at each pulse. If in register 51 the value of the compared value is less than in the memory cell, then at the output of adder 50 there is a transfer sign identical to the logical one, and at the output of element 52. - logical zero. In this case, the element 54 does not transmit a signal to write the contents of the RAM cell to the register 51 and a smaller number remains in the register. If the number in the RAM cell is less than in register 51, then the transfer sign at the output of the adder 50 is absent, the recording signal is via ele. cops 61 and 54 goes to register 51

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7

1 352369.

and a lower number is recorded.

Thus, in register 51, the smaller period value of the measured frequency is stored. After filling the counter 47, a pulse arrives at the trigger 46, which is set to the zero state, locking the element1Q 48, and the clock frequency from element 7 does not pass to the counter 47. The minimum number converted in the calculation circuit 53 of the block 56 is displayed in maximum value

. | g casting rotor speed.

Element 41 is provided for manual reading of the RAM stored in the cells. It is an RS flip-flop which, in its initial state at the output

2Q is 1. When the contacts of the key are closed, the output of the element 41 appears to open again 1. Through the elements 42 and 60, the signal enters the input C of the counter 47.

25 Pulses to start the calculator 53 come through the element OR 24 of the block 56 either from the element 59 of the block 4 in the normal mode (acceleration is zero), or from the element 60, when operating in the max-slot mode or manually retrieving information.

When operating in the memory mode (presence of acceleration, the counter 47 is not filled), the pulses arrive at both inputs of the element OR 24 simultaneously.

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45

35

Claims (1)

Invention Formula A device for measuring rotor speed parameters in transients, comprising a frequency sensor connected to a standardized pulse generator connected to an automatic speed measurement unit to which the reference frequency generator is connected to, through the frequency divider, and an indication unit with a memory register, which means that, in order to improve the measurement accuracy, a memory unit, a minimum allocation unit is inserted into the automatic speed measurement unit These additionally introduced a clock signal master and a period counter, and a calculator was additionally entered into the display unit, with the second output of the frequency divider connected to the first input of the memory block 50 55 1352369 ti and with the first input of the block of sight; speed measurement, the first input of the Jcoropo-minimum., the first output of the automatic block is connected to the first output of the block of measurement of the connection speed, the second output of the second input of the memory block, with the first input 11-unit of the third input connected to the second output - with the second input of the block output of the automatic measurement-indication unit, the fourth output - from the speed friction, the third output of which is the minimum input of the allocation unit connected to the fourth input of the pa-mau block the fourth output and the second input of the output unit Q input of the minimum selection unit, minimum friction, the fourth output of the display unit input is connected to the automatic speed measurement, the sixth output of the automatic section is connected to the fifth input of the memory speed measurement unit, and the fourth an input, the sixth input connected to n - d - to the output of the allocation unit by the mini output of the automatic modum block.