SU1348975A1 - Method of controlling multiphase inverter - Google Patents

Abstract

The invention relates to electrical engineering and can be used in a variable frequency drive. The aim of the invention is to enhance the functionality and increase the speed. This is achieved by replacing the process of calculating the phase currents before each switching of the inverter keys with logical operations, which allows to increase speed, and the use of logic devices instead of devices that perform calculation operations, simplifies the whole device that implements the proposed method. The operation of the device according to the proposed method does not depend on the parameters of the replacement circuit, their size, and the method of connecting the load, which allows to expand the functional capabilities. 3 il. with "(L 00 00 with SP

Description

This invention relates to electrical engineering and can be used in multiphase voltage inverters designed for a variable frequency drive.

The purpose of the invention is to expand the functionality, increase speed and simplify the device that implements the proposed method

FIG. 1 shows a functional diagram of the inverter that implements the proposed method; in fig. 2 is a control circuit of the inverter of FIG. 3 is a circuit for determining the moment of switching keys of the inverter.

The device (Fig. 1), which implements the proposed method, contains a three-phase bridge voltage inverter made on six 1.1-1.6 keys, shunted by reverse diodes, a three-phase load 2, a voltage inverter control unit 3 and sensors 4-6

phase currents.

t

The load 2 is powered by an inverter, the keys 1.1-1.6 of which are controlled from the control unit 3, the inputs of which receive signals U, U-i, on. t

loads determining the shape of the current and the signals UQ Uoc produced by the sensors 4-b current. Pairs of keys 1.1 and 1.2, 1.3 and 1.4, 1.5 and 1.6 are switched in antiphases.

Control unit 3 (Fig. 2) contains analog adders 7-9, comparators 10-12, blocks 13-15 for determining the signs of the error signals, block 16 for determining the moments of switching of the inverter keys, permanent memory 17, and block 18 D-flip-flops.

The outputs of the adders 7-9 are connected to the inputs of the comparators 10-12, to the inputs of the blocks 13-15 to determine the signs of the error signals and to the inputs of the block 16 to determine the moments of switching the keys. The outputs of the block 13-15 for determining the signs of the error signals and the comparators 10-12 are connected to the inputs of the D-flip-flop block 18, the common counting input of which is connected to the output of the switch-to-switch 16 moment of switching the keys 1.1-1.6 of the voltage inverter. The outputs of the 18 T) -trigger unit are connected to the control inputs of the 1.1-1.6 keys of the voltage inverter. Block 16 for determining the moments of switching keys (Fig. 3) contains a relay 19-21 with a hysteresis characteristic symmetrical about the abscissa axis. The loop width determines the specified maximum J error in adjusting the output currents of the inverter. From the relay outputs 19–21, the signals are fed to the single-oscillators 22–24. From the outputs of blocks 22-24, signals are sent to six-input

0 element AND NOT 25, from the output of which the signal and /, is fed to the input of the block 18 D-flip-flops (Fig. 2).

A device that implements the proposed method of phase control

5, the input current of a three-phase voltage inverter operates as follows.

The set U U signals, determining the shape of the currents in the load, are read in analog adders 7–9 from the DOC and Uoc signals, which are proportional to the instantaneous values of the current currents in the load phases. The output signals obtained in this case are mismatch5 dB, -uUj arrive at comparators 10-12, where they are compared with each other. At the output of comparator 10, the value of logical l (az 1) appears, if u u and logical o

0 (AZ O) if ulJ, iMJ, j. Similar to comparator 10 comparators work

11 and 12: if lb, l u, and A

0, if & U, L Ujj, if U and, and, if iU i and U,.

5 Simultaneously, the mismatch signals di, uU, arrive at blocks 13–15 of the sign definition, at the inputs of which the signals of the logical value 1 appear, if the signals received at their inputs are positive, and logical о 0, if these signals are negative. Thus, at the input of the persistent storage device 17, there is a six-bit code that carries information about the sign and the relative relative values of the signals uU, - - uUj. The first three bits of the code determine the signs of the error signals in each of the three phases, and the three following ones determine the results of their pair-wise comparison.

For example, the code 101100 means that the first and last mismatch signals

The g of the third phase is positive, and the second phase is negative; a unit in the fourth bit means that the signals in the first phase are larger than in the second, zero on the fifth,

bit means that the error signal in the first phase is less than in the third, and zero in the sixth bit means that the error signal in the second phase is less than in the third. The number of possible code values of the switch combination keys in the three-phase inverter is 24 and they characterize all possible variants of the arrangement of the error signals of all phases with respect to zero.

The selection of the desired switching combination according to the generated code occurs in such a way as to keep within the prescribed limits the control errors in all phases. For this, in contrast to the prototype, switching can occur not only in one phase, but also in two or three phases at the same time. In order to determine the load connection scheme (delta, star), the key switch combination is assigned to the generated code, which can be determined in a reasonable way. A negative voltage must be applied to the phase of the error signal, which has the largest value in the algebraic signal, and a positive voltage must be applied to the phase whose matching signal has the smallest value in this sense.

Then, in the case of a three-phase triangle load, the third phase is short-circuited, since in this case all possible combinations of applying voltage to the load phases are defined as combinations of + U; Oh, and where and is the voltage of the power source. From this it follows that then when all three error signals are negative (this is possible with six values of the switch combination code), switching of keys is possible, which cause a decrease in the error signal only in one phase - the one in which it has the maximum value.

However, if the mismatch signals in two phases are positive, and in the third phase, the signal is negative (six values of the combination codes

5 o

five

five

0

switching), possible switching, in which the error signals in two phases will be reduced.

If the load is a three-phase star circuit, all possible combinations of applying voltage to the load phases are determined by combinations of the following values of phase voltages:

± -TU; ± -T-; ± -T. In this case, the selection of the key switching combination by the generated code in accordance with the stated rule is carried out so as to cause a reduction of the error signals in two or three phases. The latter is possible if the mismatch signals are not of the same character (12 values of the code of the switch combination). If the signs of the error signals are the same, switching is possible, reducing the error signals in two phases (12 code values).

The key state table organized in this manner, depending on the values of the switch combination code, is previously written into the permanent storage device (ROM) of the inverter control circuit. When the circuit is operating, the switch combination code enters the ROM input, the value of which changes in accordance with the current values of the error signals. Each code value at the output of the ROM corresponds to a specific key switching combination.

For example, if at the output a combination 101 occurred, then the keys 1.1-1.5j 1.4 are on, and the keys 1.3, 1.2J 1.6 are off. For the case of a three-phase load connected in a triangle circuit, the information about the sign of the error signals is redundant. Therefore, the ISIS blocks depicted in FIG. 2 dotted lines are missing. In this case, the code of the switch combination is three bits. In this case, the ROM is programmed according to the table.

The table shows the states of the ROM and the keys of the inverter for a triangle load.

100 001 010110

001 010 011001

110101100110

Oil110101001

111100100101

The output state of the ROM varies in accordance with the current state of the comparators 10-12. In order to ensure the switching of keys at the boundaries of the permissible range of the error signals, the signals from the P35 outputs are fed to the outputs of the 18 B tripler unit with a common counting input, to which the U key signal is received from the 16 key switch detection unit and allows the recording of a new combination only when at least one of the signals uU, - u.Uj is out of range.

This way (in contrast to the prototype, in which, to determine the required switching combination of inverter keys, based on the parameters of the load replacement circuit, the output phase load currents are calculated for the four cases of switching in one phase at a time when the deviations of the output currents from the set ones exceed permissible value, according to the proposed method of controlling the output current of the inverter to determine the necessary combination of switching the keys of the inverter output deviation t shackles from given (mismatch signals) are compared in pairs in pairs and, based on the signs of the mismatch signals and their relative algebraic values, form a digital signal, convert it into pre-programmed I

a logical device in another

the digital signal, which at the moments when the error signal in one of the phases reaches the magnitude of the reference signal, generates an inverter key control signal that implements them

switching, reducing the error signal in as many phases as possible. This allows you to expand the functionality of the proposed method due to the fact

that the operation of the device that implements it does not depend on the parameters of the replacement circuit, their size and the method of connecting the load. Replacing the process of calculating the phase currents before each

By switching the inverter keys with logic operations to determine the required combination of inverter key switching, the performance is increased, and the use of logic devices instead of devices that perform calculation operations, simplifies the device implementing the proposed method as a whole.

50

Claims (1)

Invention Formula A method of controlling a multiphase inverter made on six switches connecting the load phases to the power supply poles with the delta load, which consists in forming the output current reference signals phase by phase, measuring the instantaneous currents of the phases load, form phase error signals by subtracting measured output values of load phase current from the output current setting signals, set the reference signal, at the moments when the reference level error signals reach the reference signal level and generate control signals to the inverter keys, characterized in that, in order to increase speed and expanding the functionality: capabilities by controlling load with variables f J R 2 fU / fjA AL K5 A Afff   I f Jul4 by the parameters, the mismatch signals of all phases are compared in pairs, the phases for which the mismatch signal is largest and smallest in algebraic value are determined, for the phase with the largest mismatch signal, a control signal is supplied to the key connecting this phase to the negative pole of the inverter power supply, and for the phase with the smallest, a key connecting this phase to the positive pole of the power supply. + U /r.j A / /. t } .S iKf fl Jk A AL K5 A Afff   I f  Unct ies} K1 Ki kz / G4 Ya5 X5