SU1343430A1 - Device for controlling read-out of graphic information - Google Patents

Abstract

The invention relates to automation and computer technology and can be used in information and computer systems for automated design, control. training, etc. The purpose of the invention is to improve the accuracy and speed of the device. The device contains a synchronizer 1, Shaper 2 clock pulses, delay elements 3-5, driver 6 input signals, switch 7, elements SHSh 8, 9, groups 10-16 of elements I, registers 17, 18, decoder 19, trigger 20, counters 21 , 22, a group of 2326 digital analog converters. The synchronizer 1 contains the generators 27 and 28 pulses, the elements AND 29-31, OR 32, 33. The shaper 2 clock pulses contains the triggers 37 and 38, the elements OR 39-43, the delay element 44 and the distributor 45 pulses. 1 il. (L with 4 CO i4 CO O

Description

The invention relates to automation and computer technology and can be used in computerized information systems, computer-aided design, control, training as control means for reading graphic information for inputting it into a computer, transferring it to a display device or to a storage system.

The purpose of the invention is to improve the accuracy and speed of the device. The drawing shows a block diagram of the device.

The circuit includes synchronizer 1, driver 2 clock pulses, the first 3, second 4 and third 5 delay elements, shaper 6 input signals, switch 7, first 8 and second 9. OR, first 10, 11 second 12, 13, third 14, 15 and the fourth 16 groups of elements And, the first 17 and second 18 registers, the decoder 19, the trigger 20, the first 21 and the second 22 counters, the first 23, 24 and the second 25, 26 groups of digital-analog converters (IDP),

Synchronizer 1 contains the first 27 and second 28 pulse generators, the first 29, second 30 and third 31 elements AND, the first 32 and second 33 elements OR, trigger 34 and counters 35 and 36, respectively, rows and frames. Shaper 2 clock and myl-. owl contains the first 37 and second 38 triggers, the elements OR 39-43, the delay element 44 and the distributor 45 pulses,

The diagram also shows the first 46 second 47 and third 48 inputs of the device, the first 49 and second 50 outputs of the device, and the first 51, 52, the second 53, 54, and the third 55 of the group of device actuators, slot 56 and 57, beam deflection units 58, driver 59 , CRT 60, quench trigger 61 and delay element 62.

The device works as follows.

The turn-on signal, inputted at input 46, sets trigger 34 of synchronizer 1 to 1, impulses from generator 27 arrive at input of element AND 29. Impulses from element AND 29 arrive at input of counter 35, at installation into O of counters 21 and 22. Increasing 1 counter code values 35 and 36 are received respectively

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through PDP 23 and 24 to outputs 51 and 52 of the device and further to control the beam of a CRT 60, and the beam changes its position on the screen of a CRT by the value of the first raster element along the OX coordinate, In this case, the pulse from the generator 27 is supplied through element 29 , elements OR 8 and 9 to the input 50 of the device and further to the installation of the trigger 61 in 1.

As a result, through the signal shaper 59, the CRT beam 60 is extinguished. The pulse from the OR element 9 through the delay element 62 sets the blanking trigger 61 to O. The beam on the CRT 60 is again illuminated. In this way, the beam is extinguished during transients in the device during the passage of signals.

Incrementing codes from the output of the counters 35 and 36 are fed to the inputs of the register 1 7 ,,

If there is a video signal at the input

48 equal

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shaper 6 on elements And 14 and 15, s, the output of the last signal records the contents of the counters 35 and 36 in the register 17 s. The output 49, the Signal from the output element

3 delay register 17 is set to O,

The pulse from the generator 27 through the element 29 on the signal from the generators of the signal 6 sets 1 trigger 20, which allows the passage of pulses from the generator 28 through the element 31,

The first impulse from the generator 28 through the E element I 31 enters the distributor 45, from the first output of which the signal through the element OR 41 sets 1 trigger 37, and the element SH 40 sets 1 trigger 38.

The pulse from the generator 28 through the element And 31, element 4 delay, the switch 7, the elements 11 and 13 are fed to the input of the counter 22, the code value of the X coordinate from the counter 22 is fed through the DAC 26 and the adder 56 to the deflection of the beam CRT 60 up along the axis OU with a smaller discrete. The first pulse from the generator 28 through the element

And 31, the elements OR 8 and 9 set the trigger 61 to 1, and the beam is quenched. The delayed signal from delay element 62 is set to trigger 61 at 0, and the beam is illuminated.

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If there is a video signal at the input 48, it goes to the element I 14 and to them. The pulse from the generator 28 through the element And 31 is written to the register 18. By a pulse from the delay element 5, the contents of the register 18 are shifted to the right by one bit.

The second pulse from the generator 28 through the element AND 31 enters the pulse distributor 45, from the second output of which through the CHI element 42 sets the trigger 31 to O, and through the OR element 43 the trigger 38 is set to O. The second pulse from the generator 28 through the element AND 31, delay element 4, switch 7, AND elements 10 and 12 increase the content of counter 21 by one, which leads to deflection of the beam along the OX axis by one sampling, blanking and illumination of the beam.

The video signal from input 48 of the device goes through shaper 6 to AND 14, the other input of which receives a pulse from generator 28 through AND 31. The signal from And 14 is recorded by the second pulse from generator 28 through And 31 element to register 18, and the delayed pulse From delay element 5, the contents of register 18 are shifted to the right by one bit.

The third pulse from the generator 28 through the element And 31 postutgats in the distributor 45 pulses. With the third output of the distributor 45 pulse through the elements OR 39 and 40 sets the trigger 38 to 1.

This more pulse through the delay element 4, the switch 7, the elements 11 and 13 is fed to the (+) input of the frame 22 counter. The output code of the counter 22 is converted to the DAL 26 into an analog signal, added to the analog signal from the DAC 24 on the adder 56 and block 58 deflects the beam on the CRT down along the axis of an opamp on one discrete, and the beam is extinguished and illuminated.

The video signal from input 48 of the device goes through shaper 6 to element 14, to another input which receives a pulse from generator 28 through element 31, the signal from element 14 is recorded by the third pulse from generator 28 through element 31 to register 18, and the delayed pulse with item 5 delayed

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the register 18 is shifted to the right by one bit.

Similarly, like the third pulse, a fourth-quarter pulse from generator 28 deviates a CRT beam down along the axis of an opamp by one sample, blanking and illumination of a CRT beam, recording a video signal into register 18 and shifting it to the right by one bit of its content.

The fifth pulse from the generator 28 through the element AND 31 enters the distributor 45 pulses, from the fifth output of which the pulse through the element OR 41 sets the trigger 37 to V, and through the element OR 43 the trigger 38 is set to O. The fifth pulse from the generator 28 through the element And 31, the element 4 delay, the switch 7, the elements And 10 and 12 is fed to the input (-) of the counter 2 lines and reduces by one the contents of the counter. This leads to the deviation of the CRT beam along the OX axis to the left by one discrete, quenching and illumination of the CRT beam.

The next video signal from input 48 is fed through shaper b to AND 14, another input of which receives a pulse from generator 28 through AND 31. The signal from And 14 is recorded by the fifth pulse from generator 28 through And 31 in register 18, and the delayed a pulse from delay element 35 causes the contents of register 18 to shift to the right by one bit.

The contents of register 18 through a decoder 19 by a signal from the fifth output of the distributor 45 pulses through a delay element 44, the fourth group of elements 16 And is outputted to output 55.

When the video signals at input 48 are zero, in any of the five cycles in register 18, the O record is recorded and its content is shifted by one bit to the right.

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The sixth pulse from the generator 28 through the element And 31 enters the distributor 45 pulses. A pulse from the sixth output of the distributor 45 is set to the O register 18, through the OR element 42 trigger 37, through the IShi element 43 trigger 38, and also the trigger 20, which prohibits further passage of pulses from the generator 28 through the element 31.

When the counters 36 and 35 are filled, the overflow signals arrive at the input of the AND element 30 of the synchronizer 1, where a signal is generated that through; the OR element 32 sets the trigger 34 to O, and the device stops reading.

Claims (1)

Invention Formula A device for controlling the reading of graphic information containing a synchronizer, the first and second control inputs of which are the first and second inputs of the device, the third control input is connected to the single trigger output, and the information outputs are connected to the information inputs of the corresponding digital-analogue transducers of the first group, the outputs which are the first group of information outputs of the device, the clock pulse generator, the counting input of which is connected to the first synchronization output the first output is connected to the control input of the switch, the second and third outputs are connected to one input of the AND elements of the first group, and the fourth output is connected to the single trigger input5 of the first counter, the counting input of which is connected to the output of one element And the first group, the second a group of digital-to-analog converters, whose information inputs are connected to the outputs of the first and second counters, respectively, the second group, and the outputs are the information outputs of the device, the first register, information inputs The ports of which are connected to the information outputs of the synchronizer, and the output is the first information output of the device, the first element Ш Ш, whose inputs are connected to the first and second control outputs of the synchronizer, and the output is connected to one input of the second element OR, the other input is connected to the third output of the synchronizer, and the output is the synchronizing output of the device, the first element of the VNIIPI Order 4825/50 Circulation 672 Random polygons pr-tie, Uzhgorod, st. Project, 4 43430 the output of which is connected to the setup input of the first register, the input driver, the input of which is the information input of the device, the second register, the synchronization input of which is connected to the first control output of the synchronizer, the setting 1Q input is connected to the fifth output of the clock pulse generator, and the output is connected to the information input of the decoder, and the second delay element, the input of which is connected to the first control output of the synchronizer, while the second control output of the sync The analyzer is connected to the installation inputs of the counters and to the input of the first delay element, which differs 20 times so that, in order to improve the accuracy and speed of the device, the second group of I elements are entered, the inputs of which are connected to the summing output of the switch and 25 corresponding outputs of the clock pulses, and the outputs are connected to the subtractive inputs of the first and second counters, respectively, the summing inputs of which are connected to the outputs of the corresponding AND elements of the first group, the inputs of which are connected to the subtractive output of the switch, the information input of which is connected to the output of the second element delays, a third group of elements AND, some of the inputs of which are connected to the output of the driver of the input signals, while others are connected to the first and second control outputs respectively, the outputs are connected to the information input of the second register, the setup input of the trigger and the synchronization input of the first register, respectively, the third delay element, whose input is connected to the first output of the synchronizer, and the output is connected to the shift input of the second register, and the fourth group of elements And , entrances to- 35 These are connected to the outputs of the decoder and clock generator, and the outputs are the third group of information outputs of the device. Subscription