SU1335977A1 - Information sorting device - Google Patents

Abstract

The invention relates to computing and can be used in specialized information processing systems, such as information retrieval systems. The goal of the invention is to increase speed. To achieve this goal, the system comprises a memory block 1 consisting of two memory nodes 4.5, a control block 3 and a block 2 for counting and sorting codes. Memory block 1 is made of memory, their devices with random access, connected by a data bus. Sorting is performed simultaneously by a group of like keys (sections), starting with the lower section. In each section, displacement addresses are first formed, and then all information words are transferred to a free memory node at these addresses. After sorting over all sections, the array will be ordered by key size in the lexicographical sense, regardless of the number of sections in the key. 2 hp f-ly, 6 ill. (L

Description

The invention relates to computing and can be used in specialized information processing devices.

The purpose of the invention is to increase speed.

FIG. 1 is a block diagram of the system — MMj in FIG. 2 is a block diagram of a random-access memory block; Fig. 3 is a block diagram of a block for creating displacement addresses; Fig. 4 is a block diagram of the control unit; figure 5 - format microcommand; figure 6 is an example, according to a screening process.

The device contains a block of memory 1 unit 2 forming the addresses of displacements and block to 3 controls.

The memory unit 1 is intended for storing a source and ordered array, for issuing keys or their parts, as well as for issuing and receiving information keys in the ordering process. Memory block 1 contains two random access memory nodes 4 and 5, an address register 6, a data register 7, a memory 8 and a memory control circuit 9. The memory management circuit 9 is a command decider for the memory node: writing address + 1 to register 6, writing data to register 7, writing (reading) information to (from) drive 8. Unit 2 is designed to store service information about the data to be sorted. an array, for counting the codes in the key handles being processed, for generating the motion addresses, and also for extracting the motion addresses in the memory nodes 4 and 5 during the motion phase.

Unit 2 (FIG. 3) contains a working register node 10, a memory node 11, a buffer register 12 and an arithmetic logic unit 13. The working register registers of the working register 10 have a constant functionality and are filled with service information when the device is loaded. The specific address of the register comes from block 3 of the control. The memory node 11 is intended to store the counting results and movement addresses. The memory node 11 is implemented according to the scheme shown in FIG.

The control unit 3 (FIG. 4) is designed to synchronize and control the operation of all system nodes and contains a switch node 14, a register 15

addresses mt krokomai 1, register of 16 microinstructions, node 17 of the memory of microinstructions, p o ovor of 18 sync pulses,

counter 19 is the length of the array, counter 20 / ears of the information word.

The system when sorted in descending order works in the following way.

In the initial state, the disordered array of information, for example, of 16 information words, is located in the memory node 4 (Fig. 4b). Memory node 5 is free. In cells 0, 1, 2, 3 there is the first information word.

The cell width is equal to the minimum addressable unit at nodes 4 and 5 of the memory, or is a multiple of it. In our example, the cell width is assumed to be one byte (8 bits).

In cells 4-7, the second information word is found, in cells 60-63, the last, sixteenth information word. The low byte of each word, located in the cells 3,7, 11 ... 63 is the first section - the section from which the sorting begins. The high byte of each word (fourth section) is in the cells O, 4 ... 60. Let the sorting be performed on the basis of the low two bytes. The service information about the disordered array is in node 10 of the working registers: code 16 is the array length (number of information words), code 4 is the length of the information word in bytes, code 2 is the key length in bytes, code 3 is the address of the first byte of the first from the beginning of the information words from which the sorting begins, code 60 is the address of the last (first from the end) information word, code 7 is the maximum code value in the group of bits (byte) of the key.

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 When the system starts working, the sorting in the first (younger) section of the key begins. The control unit 3 forms microcommands controlling the operation of the device (phi 5). During the initiation, under the control of the control field of the counting and sorting code of the microcommand, the array length code is transmitted from the work register node 10 to the control block 3. Then the first sorting phase, the distribution, i.e. calculating the volume V. free memory (necessary for placing all information words with code i in the sortable section)

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(For iipsi, all possible values of 1) in cell i of node 11 of memory of block 2. When this work is performed, the codes of the first section sequentially, starting with the lower addresses of node 4 of memory, are read and sent over the data bus to block 2 of counting and sort codes. At first, from block 2, the address 3 of the first code of the section being sorted is fed to the node 4 of the memory. The memory node 4, using the signals from control unit 3, reads at address 3 and transmits the read code via the data bus to block 2. Order is internal. The early processing of codes from memory 4 to block 2 is described below. After processing the received code, block 2 issues the address 7 of the second code of the section being sorted to node 4 of the memory. Address 7 is the address 3 of the first code, modified by the length of the information word. Memory node 4 reads at address 7 and forwards the read code to block 2 for processing. Control 3 performs a count of the number of readable codes of the section being sorted. After reading the last code of the cell 63 of the memory node 4 and transferring it to the block 2 for processing in the control block 3, the condition of the end of the counting will occur. At this point, in each cell i of block 2, where i is possible, the value of the code in the group (byte) will be the volume V; free memory, necessary for placing all information words in it, with code i in the section being sorted (Fig. 6, line 2).

V. K; WITH,

where K is the number of codes in the sortable section, equal to ij С - the length of the information word (scaling factor)

The results of the first phase are used in the second to form the addresses of the relocation type where, i.e. addresses indicating where in the free memory node the next information word should be moved from the memory node with disordered information. Movement addresses can be obtained in block 2 with several options.

In the third phase of sorting the first section for each located in

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memory node 4 (the corresponding word of the search is searched for the 5th memory word and the information word is moved to the memory node 5 at the address found. To search for the destination addresses, the codes of the sorted section are sequentially read from memory 4, starting with the highest or lowest bits , depending on the method of their formation at the second stage. If at the second stage in each cell i of node 11 of memory of block 2 the sum of the contents of all cells ii minus the length of the information word is obtained, then to search for addresses, move neither the codes of the section being sorted are successively read from the memory node 4, starting from the highest addresses, and the ordering is carried out to reduce the key code value. If in each cell i the sum of the contents of all cells i minus the length of the information word is obtained, then to search for addresses of movement the sorted section is sequentially read from the memory node 4, starting with the lower addresses, and the ordering is performed by increasing the key code. In any case, the next code i of the sorted section read from the memory node 4 is used as hell Resizing i of node 11 of memory of block 2, where there is the desired address of movement. With each reference to cell i, its content decreases by the length of the information word and again indicates the true relocation address for the next information word with a code in the section being sorted. After moving all the information words in memory node 5, a partially ordered array of the codes of the first section appears.

At the beginning of the third phase, the code of the length of the array and the code of the length of the information word are transferred from the registers of the node 10 of the working registers to the corresponding counters of the control unit 3.

In the current example, the address 63 (preserved after reading the last code of the first section) of the first one from the end of the code of the section being sorted from block 2 is forwarded via data bus to the node 4 of the memory. The code 7 read at address 63 enters block 2, where the address 12 of moving the first one from the end of the information word is read from the cell 7 of the memory node 11. Movement address 12 is sent to memory node 5, and

513

The start address 60 of the first from the end of the information word is poured from block 2 to memory node 4. Then, under the control of the control fields of the memory nodes 4 and 5 (Fig. 5), the microcommands of the control unit 3 executes the movement of the information word from the cells 60-63 of the memory node 4 to the cells 12-15 of the memory node 5. When an information word is moved from memory 4 to memory 5, the address is modified by one in the address registers of these devices, and the data from the output of memory 4 goes directly to the data input of memory 5, which reduces the time movement. After moving the entire information word, control block 3 initiates the transfer from block 2 to address 59 (formed as 63 minus 4) of the second one from the end of the code of the section being sorted. The code 7 read from the cell 59 of the memory node 4 is used as the cell address of the memory node 11, in which the transfer address 8 is written, which is formed in block 2 as 12 minus

4 more when selecting the address 12. Address

The 8 movement is transferred from the node 4 to the node 5 of the memory to the address 56 (formed as 60 minus 4) of the second information word from the end. After moving from the node 4 of the memory to the node 5 of the memory of the second from the end of the information word, the control unit 3 initiates the transfer from block 2 to the address 55 of the third from the end of the code of the section to be sorted. Code 4 of memory node cell 55 is used to select the address from the memory 11 of the memory 11 for moving the third information word from the end, and then this word is moved from the memory node 4 to the node

5 mi tees After moving the memory node 4 to the memory node 5 of the last information word, the sorting by descending of the codes of the first section is over (fig.bv). The key length code is decremented by one in block 2 and is analogous to zero. If the result is not zero, then control block 3 proceeds to sorting.

by codes of the second section.

Sorting in the second section is also performed in three phases: distribution, the formation of the addresses of the displacement and the displacement. At the same time, node 5 of memory is a sortable array, and node 4 of memory is free. Before the start of distribution

dividing the local memory cells, block 2 is zeroed out, the code 16 of the array length is transferred from block 2 to control block 3 to analyze the end of counting, and the address 3 of the first group of bits (byte) of the first section is converted to the address of the first code of the second section (reduced by one ). After this

Q preparation begins distribution. In the third section, it is performed in the same way as in the first. At the same time, the addresses of the codes of the section being sorted come from block 2 to the node 5 of the memory. Codes are read from the memory node 5 of the memory and transmitted to block 2, where the distribution is performed depending on the magnitude of the incoming codes. After a single transfer of all the codes of the second

0 sections from memory 5 in block 2 in each cell i of memory 11 of this device will have a code indicating the required size of the memory for placing all information words, co5 holding code i in the second section (fig.bg, line 2) .

The formation of displacement addresses in the second phase is accomplished in block 2. After the second phase in each cell

0 i of the memory node 11 will be recorded the address of moving the first from the end of the array of information word with code i in the second section (Fig. Bg, line 3).

The third sorting phase according to the codes of the second section differs only in that the node 5 of the memory is transmitting and the node 4 of the memory is receiving. Codes of the second section sequentially, starting with the higher addresses of the memory 5, 62, 59,

Q 54 ... 2, are read and forwarded via data bus to block 2. Each code i in node 11 of memory 2 corresponds to the address of a jumble indicating which address to node 4 of memory must be moved from node 5 of memory to an information word with the code i in the second section. Each time the cell i goes to the address of the move, its content decreases by the length of the information word. After moving all the information words from the memory node 5 to the memory node 4, the array will appear in the latter array, ordered by key from two groups of bits (bytes), although the sorting in the second section was performed without analyzing the codes of the first section (fig.bd) .

To fully arrange the source array, you need to perform as many

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sorting cyclone, how many groups of bits (sections) contains a keyword (key). The finally ordered array of information will be located in the memory node 4 or in the memory node 5, depending on whether the even or respectively an odd number of bit groups contains the key.

When sorting the information words Q, the contents of the same cell by length

in the order of increasing the key code — in the second phase, in each cell i of memory node 11, the sum of the contents of all cells 1 reduced by the length of the information word is obtained. In this case, in the third phase, when searching for displacement addresses, the codes of the sorted section are read, starting with the lowest addresses of the memory node containing the random array.

The volume of information sorted is determined by the capacity of one of the nodes 4 and 5 of the random access memory, i.e. may be equal to 1-4 bytes. The proposed system can be introduced as an integral part of the data processing system, in which it can relieve the processor from performing information sorting procedures.

Block 2 (figure 4) works as follows.

In the initial state, the service information is in the permanently distributed registers of the node 10 of the working registers. Before processing each section, all the cells of the memory 11 of the block 2 are zeroed under control of the signals from the control block 3.

In the distribution, each code of a sortable section of size i, coming from the memory node 4 to the memory node 5, is fed to the address input node of the memory 11 and thus addresses the cell i of the memory node 11. At this time, the block

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3 controls in the control field of the node RJ of the node 11 of the working registers and whose memory of the microcommand acquires for the node 11 of the memory the Read-modify write operation. The contents of cell i, the first time equal to zero, is read and fed to the first information input of the arithmetic logic node 13. The second information input of the arithmetic logic node 13 from the read operation register for the working register node 10 is specified by the control field of the microcommand working registers node. The arithmetic logic unit 13, under the control of the control field of the arithmetic logic unit, performs sums55

ku 7 node 11.pam tee. Then, the contents of the cell 6 of the memory node 11 and the R-register of the 10 working registers are read and summarized. The result is stored in the working register R- and in cell 6 of the memory node 11. Summation continues until the content of cell O is processed in memory node 11 and results are obtained as shown in Fig. 6, line 3.

When summing, there should be no overflow from the arithmetic logic unit 13. If it exists, this is a sign of an error in the device. Signal

and the result is recorded in the same cell i of memory node 11. The first code of size i, received from memory block 1, increases the content of the cell of memory node 11 by the length of one information word. The second code of i, received at an arbitrary point in time, again increases

information word. After all the codes of the sorted section arrive in the device and process them in each cell i in the memory node 11

a code equal to the product of the number of codes of size i and the length of one information word, i.e. the contents of cell i of memory node 11 indicate the size of memory required for

placing all information words with code i in the section being sorted.

In the second phase, the formation of the relocation addresses indicated in Fig.66 (line 3) is performed by summing up the results obtained in the memory node 11 in the first phase. In this case, in each cell i of the memory nodes 11, the sum of the contents of all cells ii minus the length of the information

the words. To do this in the register R; Node 10 of the working registers forms the additional code of the length of the information word. Then, the maximum code 7 of the group of bits (mainly the maximum possible code) from the node 10 of the working registers is transferred to the address input node 11 of the memory. The control signals from the control unit 3 cause reading of the contents of the cell 7 of the memory node 11 and the contents of the RJ register of the node 10 of the working registers. This information is summed to the arithmetic logic node 13, and the a-result, equal to 12, is written to the register

50

g RJ node 11 working registers and whose

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ku 7 node 11.pam tee. Then, the contents of the cell 6 of the memory node 11 and the R-register of the 10 working registers are read and summarized. The result is stored in the working register R- and in cell 6 of the memory node 11. Summation continues until the content of cell O is processed in memory node 11 and results are obtained as shown in Fig. 6, line 3.

When summing, there should be no overflow from the arithmetic logic unit 13. If it exists, this is a sign of an error in the device. Signal

 and

An error through the overflow of block 2 enters block 3 where it causes the termination of one sort of sorting,

Movement addresses can also be obtained by summing up the results obtained in memory node 11 in the first phase so that in each cell i memory node 11 the sum of the contents of all cells f is formed: i minus the length of the information word. For this, in the RJ register of node 10 of the working registers an additional code of the length of the information word is generated. Then the code O is sent to the address input of node 11, the contents of cell O of node 11 of memory 11 are summed with the contents of register RJ of node 10 of the working registers, and the result is entered into the same cell Of node 11 of memory 11 and into register R; node 10 working registers for use in the next w-1kle summation. Next, the contents of the cell 1 of the memory node 11 are summed with the new value of the RJ register of the node 10 of the working registers, and the result is entered into the cell 1 of the memory node 11 and into the RI register of the node 10 of the working registers. Summation continues until the contents of the cell are processed.

7 nodes 11 memories (mainly up to the maximum possible code in the sorted group).

The system control unit 3 (Fig. 4) operates as follows.

Pressing the Reset button in node 14 of the switches sets the system to the initial state, including the address of the first micro-command in register 15 of the micro-command address. Pressing the Start button initiates the work of the 18 sync pulse maker, which forms a series of sync pulses. With the onset of sync pulses, a sample of microinstructions from the microcode 17 memory circuit 17 begins and is fixed in the register of 16 microinstructions. From the register output of 16 microcommands, the control signals go to memory block 1 and to block 2.

The format of micro-instructions is shown in FIG. The microcommands from the microcommand memory scheme 17 are read, controlling the sorting procedures in the system.

The current sequence of microinstructions changes as the branch conditions change, i.e. when overflow signals occur;

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- from block 2 on error.

Form ula invention {and

1. A device for sorting information, contents (its memory unit, a control unit, the condition inputs of the control unit are connected to informational inputs-outputs of the first and second memory nodes of the memory unit, the first output of the control unit is connected to control one of the first inputs

and the second memory nodes of the memory block, characterized by the fact that, in order to increase speed, a displacement addresses shaping unit is entered into it, the information inputs-exits of which are connected to the control condition inputs, the displacement address formation block output connected to the input of the error sign of the control unit; the second output of the control unit is connected to the control input of the displacement addresses generation unit.

2. The POP device 1, characterized in that the memory node contains a data register, an address register, an accumulator and a memory control circuit, the information input / output of the node connected to the information inputs of the data register, the address register and the information output of the storage device the output of the data register is connected to the data input of the accumulator, the information output of the address register is connected to the input of the address of the accumulator, the control input of the node is connected to the input of the memory control circuit, which controls the first to the third codes connected to the gate entrance of the data register, to the gate of the gate and the summation of the address register, and to the gate gate of the storage device, respectively.

3. The device according to Claim 1, characterized in that the control unit contains a micro-instruction address register, a micro-instruction memory node, a micro-instruction register, an array length counter, an information length counter

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words, clock generator and switch node, with inputs 10VII unit branching connected to information inputs of the array length counter and word length counter, the first output of the switch node is connected to the reset inputs of the micro-address register and micro-register register , the first output of the sync pulse generator is connected to the strobe inputs of the micro-command address register and the micro-command register, the input of the error sign of the coi unit dinene with the stop input of the microinstructions address register, the output of the microinstructions address register is connected to the address input of the microinstruction memory node, the first output of the microinstructions memory node is 5

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59771nen with information input the address field of the next micro-command of the micro-command address register, the second output of the micro-command memory node is connected to the micro-command register information input, the outputs of the array length and information word length connects to the micro-command address branch fields, the second outputs of the register of micro-instructions are connected to the first and second outputs of the block, respectively, the third output of the register of micro-instructions is connected to the clock input of the clock generator, W The op and the third outputs of which are connected to the inputs of asynchronous loading and summing up the array length and information word length counters, respectively.

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Claims (4)

Claim 1. A device for sorting information containing a memory unit, a control unit, the inputs of the conditions of the control unit connected to the information inputs and outputs of the first and second memory nodes of the memory unit, the first output of the control unit connected to the control inputs of the first and second memory nodes of the memory unit, characterized the fact that, in order to increase speed, it introduced a block for generating movement addresses, the information inputs and outputs of which are connected to the inputs of the conditions of the control unit, the output of the sign of failure of the form block motion address generation is connected to the input of the error sign of the control unit, the second output of the control unit is connected to the control input of the movement address generation unit. 2. The device according to claim 1, characterized in that the memory node contains a data register, an address register, a drive and a memory control circuit, wherein the information input node is connected to the information inputs of the data register, address register and information output of the drive, information output of the data register connected to the data input of the drive, the information output of the address register is connected to the input of the drive address, the control input of the node is connected to the input of the memory control circuit, the control outputs from the first to the third of which are integrated with the input of the strobe of the data register, with the input of the gating and summing of the address register and with the input of the drive strobe, respectively. 3. The device according to claim 1, characterized in that the control unit comprises a micro-command address register, a micro-command memory node, a micro-command register, an array length counter, an information length counter I 1 words, a clock generator and a switch node, the inputs of the branching conditions of the block connected to the information inputs of an array length counter and a word length counter, the first output of the switch node is connected to the reset inputs of the micro-address register and micro-register, the second output of the switch node is connected to the start input of the shaper clock pulses, the first output of the generator of the clock pulses is connected to the inputs of the strobe of the register of the address of microcommands and the register of microcommands, the input of the sign of error block it is single with the micro-command address register register stop input, the micro-command address register output is connected to the address input of the micro-command memory node, the first output of the micro-command memory node is 1335977 ^s nen an information input next address field of the microinstruction register · microinstruction addresses, a second output node coupled to the microinstruction memory data input register microinstruction, the output of counter array length and information word length soedineny- with information fields branching microinstruction address input register, first and second outputs register of microcommands connected to the first and second outputs of the block, respectively, the third output of the register of microcommands connected to the clock input of the clock generator, W swarm and third outputs are connected to inputs of the asynchronous load counter and the summation of the array length and information word length respectively. NALU field field UPn yyfip field UBR field UPM field Yyn _t field Address of the next Nyaroconde ffate WP nffTh VlMUf Pale demit management entailed 5P management Management inside 6VC <Άη.5 α 0 h 8 12 No. go Λ 28 TO 36 cho W " 48 sg 56 60 FROM At b A P L w. - P I - m ε A 3 t - E in and n s T and AND > b A and - ABOUT At 5 6 3 0 ABOUT 3 J 6 ABOUT 3 3 0 J 3 4 b 5 4 At At At 5 7 3 3 5 7 At 7 7 Addresses 3V4 4th section! Old) 3rd section 2nd section 1st section (young) S ' 0 1 2 3 4 6 6 1 0 0 0 8 gh 12 At 16 60 80 60 60 52 2B No. 12 Ipsl r local memory addresses The size of memory for x-corruption. glory with Movement Addresses * coEal 0 At IN 12 16 go gh guards sg 36 40 48 52. 56 6C P £ 3 t At b - n FROM A n L iff A I - At th ABOUT At £ in and a - and n bi t - / in 6 0 1 3 6 3 3 3 5 J ABOUT ABOUT J 3 0 3 7 7 7 7 6 5 5 5 At At At At At At 3 3 Addresses ZU5 4th section 3rd section gth section 1st section 0 1 g 3 h 5 6 7 16 At 0 X Ό At IN 0 No. 44 40 40 in 8 4 0 0 At 8 12 16 guards 24 28 sg 36 bhd 48 X St 66 I At FROM t b - n A W A - 3 E m A I n E At in and A and 7 - in 0 and n b! / 6 6 5 ί J 3 ί 3 3 } about ΰ ΰ ABOUT 7 6 4 7 6 5 5 4 4 4 3 7 7 4 At 3 FIG. 6 \ BNIIIPI Order 4048/43 Circulation 672 _________ Subscription Custom polygr. ave, city of Uzhhorod, st. Project, 4