SU1332257A1 - Device for checking the quality of watch mechanisms - Google Patents

Abstract

The invention relates to instrumentation. The purpose of the invention is to increase the reliability of assessing the quality of watch movements. The device contains a clock pulse generator 1, a frequency divider 2, a synchronizing generator 3, a horizontal sampling counter 4, a vertical sampling counter 5, a measuring counter 6, a period number counter 7, an acoustic sensor 8, an amplifier 9, a driver 10, a switch 11, a multiplexer 12 address bus, random access memory 13, generator 14, video signal mixer 15, indicator 16, range switch 17, and tolerance limit node 18. The introduction of new elements and the formation of new connections between the elements of the device make it possible to objectively evaluate the instantaneous daily course of the clock mechanism and the amplitude of the oscillation of the dial, as well as to diagnose latent defects of the clock mechanism. 11 il. (L with to to eat

Description

one

The invention relates to instrument engineering and can be applied to the watch industry for controlling the quality of numerical mechanisms.

The aim of the invention is to improve the reliability of assessing the quality of watch movements.

On (}) ig.1 shows a block diagram of the device; FIG. 2 is a functional diagram of a frequency divider; FIG. 3 is a circuit diagram of a measuring counter; 4 is a schematic diagram of a shaper; figure 5 is a functional diagram of the switch; 6 is a schematic diagram of an address bus multiplexer; 1 in Fig. 7 is a schematic diagram of a generator of a scale and digitization; Fig. 8 is a circuit diagram of a range switch; Fig. 9 is a functional diagram of a node defining tolerance limits; FIG. 10 shows time diagrams; FIG. figure 11 - view of the information signals on the screen, the indicator.

The device contains a generator 1 clock pulses, frequency deli

one

Tel 2, sync generator 3, horizontal sampling counter 4, vertical resampling counter 5, measuring counter 6, period number counter 7, acoustic sensor 8, amplifier 9, driver 10, switch 11, multiplexer 12. address bus, random access memory (RAM) 13, scale generator and digitizing generator 14, video signal mixer 15, indicator 16, range switch 17 and node 18 for specifying tolerance limits. .

Frequency divider 2 contains (figure 2) frequency divider 19-21, element 2-2-2ИИ-ЗИЛИ-НЕ 22, dividers

23-25 frequencies and element 2-2-2И-ZILI- g outputs of frequency divider 2, and vONE 26.

Measuring counter 6 contains (fig.Z) binary counter 27, the elements NOT 28 and 29, the binary counter 30, the resistor 31, the element 2I-NOT 32 and the element 2I 33.

The shaper 10 contains (figure 4) the elements NOT 34 and 35, the element IPI-NO 36, the capacitor 37, the element NOT 38, - the capacitor 39, the elements NOT 40 and 41, the resistors 42 and 43, the capacitor 44, the element 2-OR- NOT 45, capacitor 46, elements 47 and 48, diode 49, and the output of the measuring counter 6 are connected to the fourth input of divider 2. The output of the acoustic sensor 8 is connected to the input of amplifier 9, the output

The CQ of which is connected to the input of the driver 10. The first output of the latter is connected to the second input of the -frequency divider 2 and the first inputs of counters 6 and 7. The output of the counter 7 is connected to the first input of the switch 11, in which the second and third inputs are connected respectively to the second and third The outputs of the driver 10, and the fourth entrance - with the output of the generator

- Q 20

 .

3322572

Stor 50 and 51, the element HE 52 and the diode 53..

The switch 11 contains (figure 5) elements NOT 54 and 55, element ZI-NOT - 56, element NOT 57, element 2-2I-2SHII 58, capacitor 59, resistors 60 and 61, triggers 62 and 63, elements 2I-NO 64 and 65, frequency divider 66 and Element + 2I-NE 67.

The multiplexer 12 (6) contains twelve elements 2-2I-2ILI-NOT 68 and the element NOT 69.

The generator 14 of the scale and digitization 15 (Fig. 7) contains the elements 2ILI-HE 70 and 71, the resistor 72, the programmable read-only memory (PROM) 73, the elements ZI-NOT 74, the counter 75, the multiplexer 76, the element NOT; 77, capacitor 78 and resistors 79 and 80.

The switch 17 ranges (Fig) contains a switch 81 and three resistors 82.

The layout of the node 18 for specifying the boundaries of the start-up (FIG. 9) contains coincidence circuits 83 and 84, switch 85, triggers 86 and 87, element 2I-NOT 88, element 89, element 2I-NOT 90, and a divider .91 frequencies.

The clock pulse generator 1 (FIG. 1) is connected to the first input of the frequency divider 2, the input of the synchronous generator 3 and the first input of the horizontal sampling counter 4, the second input of which is connected to the second output of the clock generator 3, whose first output is connected to the first counter input 5 vertical sampling, connected to the second d input with the first output of the counter 4 horizontal sampling. The second inputs of the measuring counter 6 and the counter 7 of the number of periods are connected respectively to the second and first

thirty

35

the outputs of the frequency divider 2, and the second output of the measuring meter 6 is connected to the fourth input of the divider 2. The output of the acoustic sensor 8 is connected to the input of the amplifier 9, the output

which is connected to the input of the imager 10. The first output of the latter is connected to the second input of the -frequency divider 2 and the first inputs of counters 6 and 7. The output of the counter 7 is connected to the first input of the switch 11, in which the second and third inputs are connected to the second and third outputs of the imager 10, and the fourth entrance - with the output of the generator .3

pa 1 clock pulses. The address bus multiplexer 12 is connected by the first input to the output of counter 7, the second to the output of counter 6, the third to the output of counter 5, the fourth to the output of counter 4, the fifth to the first output of switch 11, and the first and second outputs to the second and the third inputs of the random access memory (RAM) 13, in which the first input is connected to the second output of the switch 11, and the fourth input - to the first output of the driver 10. The second output of the counter 4 and the output of the counter 5 are connected respectively to the first and second, the inputs of the generator 14 scales and digitizers ki, the third input of which is connected to the first output of the synchronizing generator 3. The first input of the mixer. 15 of the video signal is connected to the output of the generator 14, the second input to the third output of the synchronous generator 3, the third input to the output of the RAM 13, and the output to the input of the indicator 16. The output of the range switch 17 is connected to the third input of the frequency divider 2 and the fourth input of the generator 14. The first input of the node 18 for setting the tolerance limits is connected to the second output of counter 4, the second input is connected to the output of counter 5, the third input is connected to the second output of clock generator 3, the fourth input is connected to the output of RAM 13, and the first and second outputs are to the fourth and fifth mixer inputs 15 video signals a.

Frequency divider 2 consists of a series-connected frequency divider 19 (divides by 6250), frequency divider 20 (divides by 2), frequency divider 21 (divides by 2), the outputs of which are connected respectively to the fifth, third, and first inputs of element 2-2 -2 AND-ZILE-NOT 22, in which the second, fourth and sixth inputs are connected to switch 17, as well as three series-connected frequency dividers 23-25 into two, the inputs of which are connected respectively to the fifth, third and first inputs of element 2-2 -2 AND-ZILE-NOT 26, in which the second, fourth and sixth inputs By connecting the switch 17. The first inputs 19-21 and dividers 23-25, connected to the first input of the shaper 10, the second input of the divider 19 is connected to the output of the generator 1, and the second input of divider 23 - to the second vy32257 4

the run of counter 6. The output of element 22 is connected to the second input of counter 6, and the output of element 26 to the second input of counter 7. Frequency divider 2 produces pulses for counters 6 and 7 with a tracking frequency determined by the selected measurement range.

10 The horizontal sampling counter 4, the vertical sampling counter 5, and the number of periods counter 7 are common binary counters. The horizontal counter 15 is sampled 15 and the vertical sampling counter 5 is designed to expand the display 16 on the screen of the motion characteristic.

clockwork, scale and its digitization- 1

2Q settings, as well as the set tolerance value of the instantaneous daily variation. Counter. 7 number of periods is used to count the number of periods for measuring the instantaneous daily variation.

25 hour mechanisms (in this case for two full turns of the anchor wheel of such periods 30).

Measuring counter 6 (fig.Z) consists of a binary counter 27,

3Q inputs of which are connected to the divider 2, the driver 10, and the input element HE 28. The outputs of the counter 27 are connected to the multiplexer 12 and the input of the element NO 29. The outputs of the elements 28 and 29 are connected to the inputs of the binary counter 30, to the inputs of which a resistor 31 is also connected The outputs of the counter 30 are connected to the multiplexer 12, as well as the inputs of the element 2И-НЕ 32 and the element 2И 33. The output of the element 35

0

45

ment 32 is connected to divider 2, and the output of element 33 is connected to the input of counter 30. Measuring counter 6 is designed to assign each information signal a numeric

code.

The acoustic sensor 8 is a piezoelectric element mounted on the case of a clock mechanism. The amplifier 9 is built according to a typical circuit, contains a linear amplifier and an amplifier with an AGC and is designed to amplify the signals of the acoustic sensor 8 and normalize them to level.

The composition of the former 10 (figure 4)

five

The elements HE 34 and 35 connected in series to the amplifier 9 are input, the output of the latter is connected to the switch 11. The amplifier 9 is connected to

also connected in series element 2IL-NOT 36, capacitor 37, element NO 38, capacitor 39, elements NO 40 and 41, the output of the latter is connected to switch 11. Resistor 42 is connected to input of element 38, and resistor 43 is connected to input of element 40. element 38 is connected to the input of element 36 and a capacitor 44 connected to the input of element 2-OR-45, to the output of which capacitor 46 are connected in series, elements 47 and 48, the output of the latter connected to divider 2 and counters 6 and 7. To the output element 45 is connected diode 49, and to the output of element 47 is a resistor 50. To The capacitor 44 is also connected to resistor 51 and to the input of Elen the included frequency divider 66 (which divides into five) and 2I-NOT 67, the output of which is connected to the trigger input 63, and the input to the output of the element 64. The inverse trigger output 63 is also connected with sync trigger 62. The output of element 64 is connected to multiplexer 12, and the secondary circuit of element 65 is connected to RAM 13. Switch 11 is used to switch the outputs of driver 10 in this way

To create for the operator

The most comfortable conditions for data transfer are 15: the information on the amplitude of balance oscillation occupies an insignificant part of the indicator screen 16. In addition, the output pulses of the switch 11 have a duration that is NOT 52, the output of which through reliable information One 53 is connected to the input of the element 47, in the RAM 13 and which does not create an output visible through which the output is connected to the input of the element 45.

The former Yu generates a control signal (first output), which sets counters 6 and 7 and frequency divider 2 to the initial state. If the acoustic sensor 8 receives noises from the clock regularly, the control signal puts counters 6 and 7 and frequency divider 2 into the operating mode. The shaper 10 also generates one information signal (second output) for each half-period of oscillation of the balance of the clock mechanism and three information signals (third output) for each half-period, which correspond to the release noise of the anchor wheel, the noise of the impulse and the falling noise of the anchor wheel. fork and anchor wheel clockwork.

The switch 11 (figure 5) consists of two elements HE 54 and 55, the inputs of which are connected to the counter 7, and the outputs are connected to the inputs of the element ZI-HE 56, the output of which is through the element HE 57 and is directly connected to the inputs of the element 2-2I- 2IL 58, two inputs of which are connected to the driver 10. The input of element 58 through a capacitor 59, to which resistors 60 and 61 are connected, is connected to the inputs of flip-flops 62 and 63, the outputs of which are connected to the inputs of elements 2И-НЕ 64 and 65, and inverse outputs flip-flops 62 and 63 are connected to their information inputs. The switch 11 includes a follower 322576

but the included frequency divider 66 (which divides into five) and element 2I-NOT 67, the output of which is connected to the trigger input 63, and the input to the output of the element 64. The inverse output of the trigger 63 is also connected to the synchronous trigger trigger 62. 64 is connected to the multiplexer 12, and the inertial drive of the element 65 is connected to the RAM 13. The switch 11 is intended for switching the outputs of the former 10 in such a manner

To create for the operator

0

fur on the display screen 16.

The address bus multiplexer 12 (FIG. 6) consists of twelve parallel-connected 2-2 and 2IL-NE 68 elements whose inputs are connected to the input and output of the HE element 69, whose input is connected to the switch 11. The inputs of the elements 68 are also connected with the outputs of counters 4-7, and the outputs with RAM 13, Multiplexer 12 connects counters 4 and 5 to the address bus of RAM 13 during reading information from RAM 13 or counters 6 and 7 during the arrival of information signals, i.e. at the time of recording information in RAM 13.

The RAM 13 is a static random access memory with a predetermined amount of information storage, in this case a memory size of 4096 bits.

The generator 14 (Fig.7) consists of parallel-connected to the switch 17 elements 2-OR-NOT 70 and 71, the second outputs of which are interconnected. The outputs of the elements 70 and 71, as well as the outputs of the counter 4 and resistor 72 are connected to the outputs of the PROM 73. The outputs of the counter 5 are connected to the inputs of the ZI-NE element 74, the outputs of which, as well as the output of the synchronous generator 3 are connected to the inputs of the counter 75 connected by multiplex - with a copy 76 and an element 77 connected to the element 74. To the inputs of the multiplexer 76 there is also connected a capacitor 78 connected to the first output of the EPROM 73, resistors 79 and 80 and outputs

five

0

five

0

PROM 73, and the output of the multiplexer 76 is connected to the input of the mixer 15.

The generator 14 of the scales and digitization is designed to create the conditions for an operative assessment of the instantaneous daily progress value by the operator, forms on the indicator screen 16 a scale in the form of a series of vertical lines and provides the digitization of this scale in the lower part of the screen in accordance with the selected measurement range.

Indicator 16 is a standard black and white television receiver.

The switch 17 ranges (Fig) consists of a switch 81, the outputs of which are connected to the resistors 82. The outputs of the switch 81 are connected to the frequency divider 2 and the generator 14 of the scale and digitization. The switch 17 serves to set the measuring range of the instantaneous daily travel in accordance with a predetermined measurement accuracy.

The node 18 for specifying the tolerance limits (Fig. 9) consists of circuits 83 and 84 of coincidence, the outputs of which are connected to the counter 4 and the outputs of the switch 85, to which the tolerance limit is set. The outputs of circuits 83 and 84 are connected to the inputs of the flip-flops 86 and 87, in which the second inputs are connected to the synchronous generator 3, and the outputs to the inputs of the element 2И-ЕЕ 88 .. The output of the latter is connected to the input of the multi-input element And 89, whose second the input is connected to counter 5, and the output is connected to mixer 15 and element 2I-NOT 90, whose second input is connected to RAM 13. The output of element 90 through frequency divider 91 (divides by 64) is connected to mixer 15. Node 18 performs tolerance control of clockwork mechanisms for an instant daily course, provides a display on the screen The indicator 16 of the set value of the tolerance of the instantaneous daily course at the bottom of the screen of the indicator 16 also generates a signal causing the screen to flash the characteristic of the clock when the measured value of the instantaneous daily course for 30 periods of balance fluctuations falls outside the set tolerance.

The device works as follows.

ten

15

20

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Before starting operation, the switch 1 7 sets the measurement range that provides the specified accuracy. With switch 17 position. the stroke of the band goes to the divider 2 and the generator 14. The oscillator 1 clock pulses, stabilized by a quartz resonator, produces clock pulses with a frequency of 2 mHz. These pulses go to the sync generator 3, on the third output of which a synchro mixture appears (sync pulses with line and field frequencies and quenching pulses of the same frequencies), which goes through the video signal mixer 15 to the indicator 16, ensuring its work At the first output of the synchronous generator 3, only personnel extinguishing pulses appear, which arrive at counter 5 and set it to the zero state, as well as to generator 14, where its counter 75 is set to the zero state (FIG. 7). At the second output of the synchronizer 3, lower quenching pulses appear, which arrive at the counter 4, set it to the zero state, and to the node 18, where its triggers 86 and 87 are set to the zero state (Fig. 8). From the generator 1, the pulses also go to the counter 4, which performs the line scan of the image. From the output of the higher bit of counter 4 (the first output of counter 4), the signal is input. to the second input of the counter 5.

With the arrival at the input of the generator 14 signals from counters 4 and 5, the signals appearing on its output form the vertical lines of the scale on the screen of the indicator 16, the width of which is determined by the size of the capacitor 78 and resistors 79 and 80 (Fig.7). When the counter 5 is filled, the signal from its output permits the generator 14 to issue pulses corresponding to their scale digitization (the signal from counter 5 permits the passage of pulses through the first input of the element 74 to the counter 75, which together with the multiplexer 76 converts the parallel digitizing code of the scale stored in the EEPROM 73, in sequential code.

The signals from counter 4 arrive at the circuits 83 and 84 of the coincidence of node 18 (Fig. 9). The same schemes 83 and 84 receive the code of the specified tolerance from the switch 85. If ko30 coincides

35

40

45

50

55

9-13 pins of the counter 4 and the switch 85 at the outputs of the circuits 83 and 84 appear signals that are fed to the flip-flops 86 and 87. The signals from the direct output of the flip-flop 86 and the inverse of the flip-flop 87 come to the element 88 and from it input element 89, which also receives a signal from the counter 5. When. filling the counter 5, the signal from its output permits the passage of the signal from the output of the element 88 through the element 89 to the mixer 15, providing the illumination of the tolerance limit, as well as the element 90, on the screen of the indicator 16.

Before installing the clock mechanism on the sensor 8, the first output of the driver 10 sets the signal from the level of the logical unit that sets the frequency divider 2, the counter 7 and the RAM 13 to zero state

and the counter 6 is in the state corresponding to half of its capacity, in this case 48. This is necessary so that the characteristic of the movement of the clock mechanism on the indicator 16 starts from the middle of the upper part of the screen a. On the second and third outputs of the driver 10 signals are missing

When the checked clock mechanism is connected to the acoustic sensor 8, the acoustic noise of the clock mechanism (Fig. Ia) appears at the output of the latter, which enters the input of amplifier 9, where it is amplified and normalized in amplitude using the AGC circuit of amplifier 9. From the output of amplifier 9 The signal (Fig. 10b) is fed to the input of the imaging unit 10, which, by this signal, outputs a control signal (Fig. Iuv) synchronously to its first output (Fig. Iu.V), setting the frequency divider 2 and counters 6 and 7 to the working state, and the information input

RAM 13 is in the state of logical unit. At the second input of the imaging unit 10, an information signal appears corresponding to the release noise of the anchor wheel (Fig. South), and on the third output - three information signals

. corresponding to the release noise, the noise of the impulse and the falling noise of the anchor wheel (FIG.). From the server 1, the output of the RAM 13 appears

Nala

the pulses which, having passed through the video signal mixer 15, carry out

the house of the control signal from the first vygg backlight of the indicator screen 1b. The input of the shaper 10 frequency delimiters from the output of the RAM 13 is received

also, the element 90 Wela 18 sets the tolerance limits (Fig. 9). If character 2 performs the frequency division of the clock pulse from generator 1 in accordance with the selected

The timing of the clock goes beyond the mouth

ten

the range of measurement set by switch 17. When setting switch 81 to position a, corresponding to a range of ± 6 minutes, frequency divider 2 provides a division by 6250 for counter 6 and 1.2x10 for counter 7, with .transfer switch 81 to position b 12 min range, providing Q

five

0

thirty

50

division is respectively 12500 for the counter 6 and 4, for the counter 7, in the position in the range J 24 min - by 25000 for the counter 6 and 19.2 "10 for the counter 7 (Fig.8 and 2).

The signals from the outputs of the higher bits of the counter 7. Through the encoder on the elements 54-56 (Fig. 5) define the algorithm of the switch on the elements

57 and 58 so that the output element

58s from the 1st to the 4th and from the 9th to the 30th measurement periods there is one Impulse for the half-cycle of the balance, corresponding to the release noise of the anchor wheel, and from the 5th to the 8th measuring period - three pulses corresponding to the release noise, the noise of the pulse and the falling noise of the anchor wheel. These pulses through a differentiating circuit on a capacitor

59 and resistors 60 and 61 are supplied

triggers 62 and 63, which, together with elements 64, 65 and 67 and frequency divider 66 (divides by 5), generate pulses of the required duration for multiplexer 12 and RAM 13. - At the moment of the appearance of these pulses

multiplexer 12 connects the address inputs of the RAM 13 to the outputs of counters 6 and 7, the RAM 13 goes into recording mode. At the end of the pulse, the RAM 13 enters the readout mode and its address inputs are connected via multiplexer 12 to counters 4 and 5. Thus, the measured information is represented as the address of the RAM 13, which is recorded 1. During the reading of information, when the state of the counters 4 and 5 coincide with the address at which in RAM 13 the record35

45

by 1, at the output of the RAM 13 appear

If the clock moves beyond the set tolerance, then at the entry of element 90, frame frequency pulses appear, which through divider 91 (divides by 64) enter the mixer 15, which causes the characteristic of the clock to flash at a frequency of 8 Hz (f, 50 Hz; 0.78125 Hz).

In general, on the indicator screen 16 have full information about the quality of the checked clock mechanism.

If the clock is blown exactly, the stroke characteristic looks like that shown in Fig. 11a, while the balance oscillation amplitude is normal. In Fig. 116, it is seen that the clock is in a hurry for 7 minutes, as this exceeds the established tolerance (solid horizontal lines in the left and right parts of the screen), the characteristics flash at 0.8 Hz. In Fig. 11b, the clock is lagging A min, pumping and amplitude of balance fluctuations are normal. In Figure 11g, the clock is accurate, but the pumping and amplitude of balance oscillations have significant deviations (a large distance from the main lines of the diagram indicates that the pumping is greater than the established rate, a large distance between the left main line of the diagram and the extreme right short line indicates underestimated amplitude of balance oscillations). On fig.11d, the clock lags by 3 minutes, which does not exceed the frequency divider's adaptations, respectively, a clock pulse generator and a range switch are connected, and the second output of the switch is connected to the first input of a random access memory, which is improve the reliability of assessing the quality of clockwork mechanisms; a count of the number of periods, a vertical sampling counter, a horizontal sampling counter, an address bus multiplexer, a generator and digitizing generator, a node, setting boundaries tolerances and video mixer, with the first and second inputs of the counting of the number of periods connected

35

The tolerance, pumping out and amplitude of balance oscillations are normal, but the line of the diagram is intermittent - the tooth of the anchor wheel is damaged. On fig.lie, the instantaneous daily travel exceeds service — Q corresponds to the first output, the formed tolerance — the characteristic of the world viewer and the first output of the frequencies flashes; moreover, one of the lines has an irregular (scattered) shape, which means that the pull of one from pallet. In FIG. IG, irregular stroke, large deviations of the clock due to the unregulated length of the spiral (the Vibration Spiral operation is poorly performed). In FIG. 11, the clocks do not exceed the established tolerance, but the distance between the lines is not the same — the radial beats of the anchor wheel. In FIG. PI lines with deviations left and right, the interaction of the main wheel system is disturbed. In FIG. Ik, the scatter of lines composed of irregular segments with a chaotic arrangement of points caused by

a knock of balance - the steepest moment of the winding spring is overstated. In Fig. 11l, a wavy line is a large gap in the axles of the anchor fork or balance. In Fig. 11m, irregularly shaped wavy lines disrupt the interaction of the anchor wheel tribe with the second wheel.

Claims (1)

Invention Formula A device for controlling the quality of clockwork mechanisms, which contains a clock pulse generator, a frequency divider, a clock generator, a measuring counter, a range switch, a random access memory, a switch, an indicator and a series-connected acoustic sensor, an amplifier, and The inputs of the frequency divider are connected to a clock pulse generator and a range switch, respectively, and the second switch output is connected to the first RAM input, which is because, in order to improve the reliability of estimating the quality of clock mechanisms, vertical sampling counter, horizontal sampling counter, address bus multiplexer, generator and digitizing generator, node, tolerance limits, and video mixer, the first and The second inputs are the counting of the number of periods connected corresponding to the first output of the former and the first output frequency 0 five the divider and the output of the counter for the number of periods are connected to the first input of the switch and the address bus multiplexer; the first and second inputs of the measuring counter are connected respectively to the first output of the driver and the second output of the frequency divider, the second input of which is connected to the first output of the transformer, the first output of the measuring counter is connected to the second input of the address bus multiplexer, and the second output of the measuring counter is connected to the fourth input of the frequency divider, the fifth input of the address bus multiplexer connected to the first output of the switch, and the first and second outputs; bus address multiplexer connected 13 the second and third inputs of the random access memory, for which the fourth input is connected to the first output of the driver, respectively, the first and second inputs of the horizontal sampling counter are connected respectively to the output of the clock generator and the second output of the clock generator connected by its input to the output of the clock generator, the first output horizontal sampling counter connected to the second input of the vertical sampling counter, in which the first input is connected to the first at the output of the synchronous generator, and the output of the vertical sampling counter is connected to the third input of the address bus multiplexer, the first input of the node to define the boundaries and the second input of the cabinet and digitizing generator, the second output of the horizontal sampling counter is connected to the fourth  the address bus multiplexer input, the second input of the node specifying the tolerance limits, and the first input of the scale0 generator 3225714 and digitization, the third input of which is connected to the first output of the synchronous generator, the output of the range switch is connected to the fourth input of the scale and digitization generator, the output of which is connected to the first input of the video signal mixer connected to the third output of the synchronous generator, the third input of the video signal mixer is connected c) the output of the random access memory and the fourth input of the node specifying the tolerance limits, and the output of the video signal mixer is connected to the indicator input, the second output is sync The rator is connected to the third input of the node specifying the tolerance limits, the first and second outputs of which are connected respectively to the fourth and fifth inputs of the video mixer, the second and third outputs of the imaging unit are connected respectively to the second and third inputs of the switch, whose fourth output is connected to the generator clock pulses. five 0 25 From cpapMupoS.JO From genvrat. one From pies - (and / 1uch, W counter S. Lp ffeAt / order From d) termica Yy (/ W YU 3Z / R sf / ume / rroZ 33 -1 vr icu / ium, 9 "IL nor- rcS.:/, H divider It cvemtfuffoft SuT CV An: 4 8 I S6 S "7 M ( well be t / kcopy 12 65 81 a Fig.8 / mix 15 -0 +% Phi.1 To dividers 2 and generator 14 From cw / nvu / ta 5 From cvemvuffOj --- I / ss Tbp-I 31 one / 77 simhrogene. J Qm gjy / 3 jn JL JiniL -C || and SHSh. H SHSh. FIG. ten Editor I.Nikolaychuk Compiled by S.Shakin Tehred M. Proofreader S. Shekmar Order 3829/41 Circulation 370. Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company. Uzhgorod, ul, Project, 4 Fi.11