SU1325671A1 - Spectrometric pulse generator - Google Patents

Abstract

The invention can be used to configure and test the blocks that make up the spectrometric apparatus. The purpose of the invention is to improve the accuracy of setting the amplitude of pulses and expanding the functionality of the generator, achieved by introducing pulse generation modes with linearly varying amplitude, with amplitude changing with a certain increment, generating square pulses and generating second pulses with the possibility of delaying the second pulse relative to first. The generator is implemented on a sixty-two block of logic elements, triggers and counters, including a digital-to-analog converter (DAC). The error in setting the pulse amplitude in the generator is 0.024% when using a 12-bit DAC, which is about 8 times less than the error in setting the amplitude in the prototype. 2 hp f-ly, 5 ill. SL

Description

The invention relates to a pulse technique and can be used to tune and check the units included in the spectrometric apparatus.

The purpose of the invention is to increase the accuracy of setting the pulse amplitude and expand the functionality of the device by introducing pulse generation modes with a linearly varying amplitude, with an amplitude varying with a certain increment, generating rectangular pulses and paired pulses with the possibility of delaying the second pulse relative to the first one.

FIG. a functional diagram of the spectrometer pulse generator is presented; Fig. 2 shows timing diagrams for the operation of the device; FIG. 3 is an example of a specific implementation of the frequency divider unit; 4 shows an example of a specific implementation of a control unit; figure 5 - presents examples of the specific implementation of the noise generator and the differential frequency meter unit.

The device contains a clock generator 1 and pulses, the output of which is connected to the clock input of the block 2 pulse frequency dividers and the first input of the first element AND 3. The first output 4 of the unit 2 is connected to the first input of the second element And 5 and the clock input of the first D-trigger 6, the second output 7 of the block is the 2nd by the first input of the third element AND 8 and the first input of the fourth element And 9, the third output 10 of the block 2nd by the first input of the fifth element And t1, the fourth output 2 of the block 2nd by the first input of the element IS-NOT 13 , The outputs of the elements And 3 and 5 through the first element OR 4 connections enes to a clock input of the binary counter 15 pulses, the outputs of which are connected bitwise with the inputs of digital-to-analog converter 16 (DAC). The output of one of the bits of the binary counter 15 is also connected to the first input of the sixth And 17 element. The first output 18 of the control unit 19 is connected to the second input of the first And 3 element, the inverse input of the third And 8 element, the first input of the seventh And 20 element and the second input of the sixth element And 17, the second output 21 of the block 19 - with the second input of the fourth element And 9 and the control input lane

the second relay 22, the third output 23 of the block 19 - with the second input of the second element And 5 and the second input of the fifth element II; the fourth output 24 of the block 19 - with the information input of the second D-flip-flop 25, the fifth output 26 of the block 19 - with the input reset D-flip-flop 25, the sixth output 27 of block 19 - with the first inputs of the second and third

elements OR 28 and 29, the seventh output 30 of block 19 is with the control input of the first delay element 31, the eighth output 32 of block 19 is with the control input of second turn 33. Output

The second element AND 5 is connected to the first input of the fourth element OR 34, the second input of which is connected to the output of the sixth element AND 17 and the clock input of the D-flip-flop 35. The output of the fourth element OR 34 is connected through the second delay element 36 to the first input of the sixth element OR 37 and through the fifth delay element 38 with the second input of the seventh element AND 20, the output of which is connected to the second input of the second element OR 28, the output connected to the reset input of the third D-flip-flop 35. The direct output of the second D-flip-flop 25 is connected to the second

the input of the third element And 8, the output of which is connected to the second input of the fifth element OR 37, the second input of the block 39 of the differential frequency meter and through the first delay element 31 to the third input of the fifth element OR 37. The output of the fourth element And 9 is connected to the fourth input n That element I-LTH 37, inverted output of the second D-flip-flop 25 with the third input of the second element And 5, the data recording input of the D / A converter 16 and the third input of the fifth element II P whose output is connected to the input. reset RS-flip-flop 4P reset input

and the first D-flip-flop 6 and the second input of the third element OR 29, the output of which is connected to the reset input of the binary counter 15 and the reset input of the binary-decimal counter 41.

The direct output of the first D-flip-flop 6 is connected to the second input of the element AND-NOT 13, the output of which is connected to the clock input of the binary-decimal counter 41. Inverse VBGKHOD first

D-flip-flop 6 through the fourth delay element 42 is connected to the input of the register entry 43 ,. the inverse of the output of the third D-flip-flop 35 - with the third input of the first element AND Z. PEN.

3

The RS-flip-flop 40 through the second pulse shaping unit 44 is connected to the clock input of the second D-flip-flop 25, the inverse output E5 of the flip-flop 40 is connected to the fourth input of the second element And 5 and the information input of the first D-flip-flop 6, Dov binary decade 41

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through the register 43 and the decoder 45 with the fourth output 12 of the block 2

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stored on the bottom with the inputs of the block 46 of the display. The output of the noise generator 47 and the output of the element OR 37 through the switch 48 are connected to the inputs of the pulse width imager 49 and the one-shot 50, the outputs of which through the first contact group of the relay 33 are connected to the control input of the clock switches 51. Drive block 39

:: connected to the control input of the generator 47, the output of the block 39 connected to the first input. The output of the DAC 16 and the output of the generator 52 of linearly varying voltage through the contacts of the relay 22 are connected to the input of the converter 25, the voltage 53 is the current whose output unit 51 is connected to the input of the operational amplifier 54 and the first terminals of the resistor 55 and the parallel-connected capacitor 56 and potentiometer 57. The second outputs of the capacitor 56, potentiometer 57 and resistor 55 through the second group of contacts of the relay 33 are connected to the output of the operational amplifier 54, by the output of the waveform generator 58 and the first input of the comparator 59, the second input of which is connected to the output of the source 60 of the adjustable reference voltage. The output of the imaging unit 58 through a buffer amplifier 61 is connected to the output 62 of the device, Starter. the comparator 59 through the pulse shaping unit 63 is connected to the installation input to the G RS flip-flop 40,

The block 2 of frequency dividers (FIG. 3) contains pulse frequencies connected in series with the first PS, fifth dividers 64-68, the first input of the first element AND 69 is connected to the input of the first divider 64, the outputs of dividers 65-68 are connected respectively to the first inputs of the elements AND 69-74, the outputs of which through the element OR 75 and the first driver 76 of the pulses are connected to the second output 7 of the block 2. The second inputs of the elements 69-74 are connected to the corresponding contacts 77 of the multi-position switch 78,

output divider 65 through the third pulse shaper 88 — with the first output 4 of block 2, output divider 68 through the seventh pulse frequency divider 89 and the fourth pulse shaper 90 — with the third output 10 of block 2. Frequency divider 64 and the first element input And (69 are connected to

clock input unit 2. g

The control unit 19 (Fig. 4) contains the first to the fourth switches 91-94, the first contacts of which are connected to the common bus and the second contacts through the resistor 95 to the voltage source. The movable contact of the first switch 91 is connected to the first input of the first element AND- NOT 96, the second input of which is connected to the moving contact of the second switch 92, the input of the first element AND 97, the first input of the first element 98 and the third output 23 of the block 19. The output of the element I- HE 96 is connected to the second input of the element AND 98 and

35 by the fourth output 24 of the block 19. The third input of the first element I 98 is connected with the output by the first integrator of the chain 99, the input of which is connected to the voltage source. Exit first

40 of the element AND 98 is connected to the fifth output 26 of the block 19, the first input of the second element AND-NOT 100 is with the movable contact of the third switch 93, the second input of the second element AND-NOT 100

45 with the output of the first element NOT 97 and the first input of the second element AND 101, the output of which is connected to the second output 21 of the unit 19. The output of the second element AND-NOT 100 is connected to the second input

50 of the second element I 101 and through the second element NO 102 with the first output 18 of the unit 19. The movable contact of the fourth switch 94 is connected with the seventh output 30 of the unit 19. The movable terminal

55 cycle of the fifth switch 103 through a resistor 104 is connected to a voltage source, and the first contact is connected to the eighth output 32 of the block 19, the first input of the third element 105 is connected to the first

5671.

as well as through resistors 79-84, respectively, with a palm bus. A moving contact of the multi-position switch 78 is connected via a seventh resistor 85 to a voltage source. The output of the first divider 64 through the sixth divider 86 pulse frequency and the second driver 87 pulses connect the fourth output 12 of block 2

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output divider 65 through the third pulse shaper 88 — with the first output 4 of block 2, output divider 68 via the seventh pulse frequency divider 89 and the fourth pulse shaper 90 — with the third output 10 of block 2. The splitter 64 input and the first input of the And element (69 are connected with

clock input unit 2. g

The control unit 19 (FIG. 4) contains the first to fourth switches 91-94, the first contacts of which are connected to the common bus and the second contacts through the resistor 95 to the voltage source. The movable contact of the first switch 91 is connected to the first input of the first element AND- NOT 96, the second input of which is connected to the moving contact of the second switch 92, the input of the first element AND 97, the first input of the first element 98 and the third output 23 of the block 19. The output of the element I- HE 96 is connected to the second input of the element AND 98 and

5 by the fourth output 24 of the block 19. The third input of the first element AND 98 is connected with the output of the first integrator of the chain 99, the input of which is connected to the voltage source. Exit first

0 of the element AND 98 is connected to the fifth output 26 of the block 19, the first input of the second element AND-NOT 100 is with the movable contact of the third switch 93, the second input of the second element AND-NOT 100 5 with the output of the first element HE 97 and the first input of the second element AND 101, the output of which is connected to the second output 21 of block 19. The output of the second element NAND 100 is connected to the second input

0 of the second element I 101 and through the second element NO 102 with the first output 18 of the unit 19. The movable contact of the fourth switch 94 is connected with the seventh output 30 of the unit 19. The movable terminal

5 cycle of the fifth switch 103 through a resistor 104 is connected to a voltage source, and the first contact is connected to the eighth output 32 of the block 19, the first input of the third element 105 is connected to the first 51

By a common contact of the sixth switch 106 and through a resistor 107 with a voltage source, the second input of the third element I 105 - with the code of the second integrating chain 108, whose input is connected to the voltage source. The output of the element 105 is connected to the sixth output 27 of block 19

Block 39 of the differential frequency meter (Fig. 5) contains an RS trigger 109, the direct output of which is connected to the input of the integrator 110, the output of which is the output of block 39. The installation input of the RS flip-flop 109 is connected to the first input of block 39, and the input reset - with the second input of block 39.

The noise generator 47 (Fig. 5) contains a noise source 111, which is a reverse biased emitter-high-frequency transistor base. The output of the source 111 is connected via an amplifier 112 with a first input of the comparator 113, the output of which is the output of the generator 47. The second input of the comparator 113 is connected to the control input of the generator 47.

The generator works as follows.

After power is turned on, the outputs 26 and 27 of the block 19 generate pulses of the initial installation of the binary counter 15, the binary-decimal counter 41 and the D-flip-flops 25 and 35, the further operation of the generator depends on the position of the switch 48 and the switches 91-94, 103 and 106 block 19 (Fig.4),

The generator operates in the following seven modes: setting the required pulse amplitude, generating spectrometric or rectangular pulses, generating periodic pulses, generating statistical pulses, measuring the integral and linearity, measuring differential nonlinearity, generating paired pulses.

In all modes of operation, the generator can produce either spectrometric or rectangular pulses.

Block 2 converts the frequency of the clock generator 1 into a series of frequencies necessary for the generator to operate in all modes. On fig.Z shows a functional diagram of this unit, provided that the frequency of the clock generator 1 is equal to 100 kHz. At exit 7 post

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impulses are falling at the frequency specified by switch 78 (FIG. 4), at output 10 - impulses with a frequency of 2 Hz, which set the installation cycle in the 5 setting mode. The required amplitude, at output 4 - pulses with a frequency of 10 kHz, which are necessary for operation in the setting mode, output 12 - pulses with a frequency of 25 kHz, which are used in the mode of setting the required amplitude. The pulses at the outputs of block 2 are normalized in duration with the help of formers 76, 87, 88 and 90 (Fig. 4).

f5 Mode of installation of the required amplitude.

This mode of operation is carried out in conjunction with the mode of generation of periodic pulses, therefore,

20. Switch 48 must be in the position shown in FIG. For definiteness, we assume that the generator generates spectrometric pulses. In block 19, switches

25 are installed: in the following (Fig. 4) positions: switches 91 and 92 - to the bottom, switch 93 - to any position, switches 94, 103 and 106 - to the upper position. Then

30 at outputs 23 and 27 is set to logical 1, at outputs 24, 26, 21, 18 and 30 - logical O. Since there is no voltage at output 32, relay 33 does not trigger, and

Its contacts are in the position shown in Fig., the output of the driver 49 is connected to the control input of the block 51, and the capacitor 56 and the potentiometer 57 40 connected in parallel with the output of the operational amplifier 54. The amplitude of the spectrometer pulses is required by the source 60.

45 If the RS-flip-flop 40 is not reset, after the power is turned on, the cycle of setting the required amplitude begins with the arrival of a pulse from the output 10 of block 2, which passes through the element 11 and sets the RS-flip-flop 40 to the initial state (Fig .2a). If the RS trigger 40 is reset after power up,

55 then the cycle of installation of the required amplitude begins after the end of the initial installation pulses at the outputs 26 and 27 of block 19. As a result, the pulse from output 4 (Fig. 26),

unit 2, passed through the element And 5 and the element NLI 14, is fed to the clock input of the binary counter 15, writing down to its initial state one. The change in the state of the input bits of the binary counter 15 is converted by the DAC I6 to the changed level of its output voltage (Fig. 2B), which is fed through the contacts of the relay 22 to the input of the converter 53, which converts this voltage level to the corresponding current level. At the same time, the pulse from the output of the element AND 5 passes through the element OR 34, is delayed for the duration of transients that occur at the output of the DAC 16 when it is switched, by element 36 (for a 572PA2 series DAC, the delay time is 45 µs) and enters the input of the element OR 37 The pulse from the output of the latter (Fig.2) passes through the switch 48 to the input of the imaging unit 49,

; The code of the binary counter 15 is in the binary-decimal code, which then

which forms duration-stable pulses. Block 51 open-. 25 is converted by the decoder 45 into a code equal to the duration of the im- (seven-segment indicators. The generator at the output of the driver 49. The current from the output of the converter 53 through the public keys of the block 51 is fed to

The input of the operational amplifier 54 and 30 D of the generator is equal to 10 V, which corresponds to the charging of the capacitor 56, which corresponds to the standard on spectrometry, which leads to an increase in the voltage at the output of the operational amplifier 54, and this is done in the window. Since the maximum amplitude of the pulses generated by the output equipment, using a 12-bit DAC 16, it is necessary that 4000 pulses fill in binary digital counter 15 with 2, for the same time 10000 received for binary-decimal 41. pulses. Therefore, if the frequency of the pulses at the output 4 of the unit 2 is 10 kHz, then during the control pulse, the current switches in the block 51 are closed and the capacitor 52 is discharged through the potential-. Cyometer 57. Thus, at the output of the operational amplifier 54, pulses are formed with a front equal to the duration of the pulse at the output. Forming of 40 pulses at the output 12 should be equal to 49, and a drop proportional to 25 kHz. the constant time of the chain consisting of a capacitor 56 and a potentiometer 57 (FIG. 2d). Front duration should

At the beginning of the cycle of setting a given amplitude, D-flip-flop 6 is set to 1 by the first pulse from output 4, to be much shorter than the decay time, 45 Allowing it to pass through is determined by the appropriate choice of the duration of the generated pulses at the output of the driver 49 and the time constant of the chain capacitor 56 and potentiometer 57 fna- 50 starts counting the time dyadic de- example, the front 20 is not constant and spa adic counter 41 with a torque of HA and 10 microseconds). The pulses of this form of the beginning of the counting of a binary counter 15 are called spectrometric, because (fig. 2z, i). At the moment when the same shape is reached, the pulses on the output pulse of the operating amplitude of the charged preamplifier have 55 54 the amplitudes of the slave; With the arrival of each, the comparator 59 is set; the unit is set to the RS-flip-flop 40, a single state of the RS-flip-flop 40, to the clock input of the binary counter-inverse output of which each subsequent D-trigger input 6 served

the pulse at the output of operational amplifier 54 is increased by a single increment until it is comparable with the voltage at the output of source 60. In this case, the comparator 59 gives up, at its output a positive voltage drop appears, from which the block 63 forms a short signal setting in

a single state of RS-trIGG 40. At the inverting output of this trigger, a logical O appears, which prohibits the passage of pulses from the output 4 of block 2 through the element 5.

The contents of binary counter 15 after this time point do not change, and subsequent pulses generated at the output of operational amplifier 54 have the same amplitude. To indicate the magnitude of the set amplitude, it is necessary to convert

; The code of the binary counter 15 is in the binary-decimal code, which then

converted by the decoder 45 into a code (seven-segment indicators. In the

converted by the decoder 45 into a code (seven-segment indicators. In the

This is done in the following way. Since the maximum amplitude of the pulses formed at the output of the 30 D generator is 10 V, which corresponds to the standard for spectrometry

With the use of a 12-bit DAC 16, it is necessary that for 4000 pulses, binary counter 15 is filled to cix 2, during this time, 10 000 pulses were received on the binary-decimal counter 41. Therefore, if the frequency of the pulses at output 4 of block 2 is 10 kHz, then often the pulses at output 12 should be 25 kHz.

At the beginning of the cycle of setting the specified amplitude, D-flip-flop 6 sets the pulses from output 12 through the IS-NOT 13 element to the clock input of the binary-decimal counter 41, Thus, a synchronous O and the next pulse from the output A of the block 2 of frequency dividers D- trigger 6 is reset. Logic O at the direct output of D-flip-flop 6 prohibits further passage of pulses from the output J 2 of the block 2 frequency dividers through the NAND 13 element to the clock input of the binary-decimal counter 41, whose code corresponds to the magnitude of the set amplitude. The positive differential from the inverse output of the D-flip-flop 6 by the element 42 is delayed by the time of the end of the transient processes in the binary-decimal counter 41. At the delay element 42, a short signal is generated by which the code accumulated in the binary-ten counter 41 is written to the register 43. Storing the accumulated code in register 43 eliminates the flashing of numbers in the display unit 46.

Changing the output voltage of the source 60, for example, using a potentiometer, the slider of which is connected to the input of the comparator 59, can change the amplitude of the pulses at the output of the operational amplifier 54, and each cycle of setting the required amplitude starts with the arrival of a pulse from the output 10 of the block 2 frequency dividers which sets the RS-flip-flop 40, D-flip-flop 6, binary counter 15 and binary-decimal counter 41.

In order to prevent the code defining the set amplitude from being reset, the switch 91 is set to the Operation position (Fig. 4). Then, at outputs 24 and 26 of control unit 19, logical 1 is set. After the comparator 59 is triggered, the instant of the end of the setup cycle is determined, the RS flip-flop 40 is set to one state. The positive differential at its forward output is converted by the block 44 into a short signal which sets the D-trigger 25 to a single state, since now logical 1 from outputs 24 and 26 of block 19, logical O about the inverse output of D-flip-flop 25 prohibit 55 of control 51 and 51 is supplied to its information input and reset output. V1 the passage of pulses from output 4 to the feedback of the operational amplifier 2 through the element 5, and to the input of the bodies 54 of the resistor 55. The block 51 of the DAC 16 opener records the duration of one-code pulse c. the output of the binary counter 15 of the novibrator 50, during this time, the internal register of the CLP 16. Logical O from the inverse output of the D-flip-flop 25 also prohibits the passage of pulses from output 10 through the element 11 to reset the RS-flip-flop 40, binary counter 15 and binary-dec 41, Logic 1 at the direct output of D-flip-flop 25 allows the passage of pulses from output 7

block 2 frequency dividers through the element And 8, the element OR 37, the switch 48 and the driver 49 to the control input of the block 51,

As a result, the generator produces spectrometric pulses of a set amplitude, the magnitude of which is indicated by the display unit 46, at a frequency set by the switch 78 in block 2 (FIG. 3).

In order to change the set amplitude, it is necessary to switch the switch 91 in block 19 to the Installation position (lower in FIG. 4). Then the logical O from the output 26 of block 9 arriving at the reset input of the O-flip-flop 25 sets it to the zero state , thereby allowing the passage of a pulse from output 10 through the element 11 to reset

RS-flip-flop 40, D-flip-flop 6, binary-decimal counter 41 Logical O from the direct output of D-flip-flop 25 prohibits the passage of pulses from the output 7 of block 2 through the element 8. 8. The further setting of the maximum pulse width is similar to that described.

The process of setting the amplitude in the formation of rectangular pulses

does not differ from the process of setting the amplitude of the spectrometric pulses.

The mode of generation of spectrometric or rectangular pulses.

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The shape of the pulses generated by the generator is set by the switch 103 in block 19 (Fig 4). In order to form the rectangular pulses, the switch 103 is set to the lower (Fig. 4) position. Relay 33 from output 32 of block 19 is energized, the relay is energized, which causes the output of the one-shot 50 to close

It i

The mein through the resistor 55 flows a current from the voltage converter 53 - a current, causing a voltage drop across this resistor, which is applied to the output of the operational amplifier 54, since its input has zero potential. As a result, a square-wave pulse with a front is formed at the output of the operational amplifier 54, now at the rise time of the operational amplifier 54, and with a duration equal to the pulse duration of the single-oscillator 50.

The periodic pulse generation mode is explained in the description of the first mode.

The mode of generating statistical pulses.

The generation of statistical pulses is understood as the generation of pulses with a fixed amplitude, the moments of the occurrence of which are subject to the Poisson distribution law. A pulsed flow of this type imitates a real pulsed flow of recorded signals in a nuclear-physical experiment.

To implement this mode of operation, it is necessary to set the required amplitude of the pulses in the mode of setting the amplitude of the pulse. Then, the output of the generator 47 is connected via the switch 48 to the inputs of the imaging unit 49 and the one-oscillator 50. The noise voltage source I1 is a reverse biased emitter-to-base transistor, it is amplified by the amplifier 112 and fed to one of the inputs of the comparator 113 (Fig. 5) .

The S-and R-inputs of the trigger 109 in block 39 of the differential frequency meter of Fig. 5) are respectively supplied with statistical pulses from the generator 47 and periodic pulses from the output of the AND 8 element, the frequency of which is controlled by the switch 78 in block 2. Change the frequency of the periodic pulses, you can adjust the average frequency of statistical pulses on the generator code 47 (disabling the instantaneous frequency of statistical pulses from its average value is distributed according to the Poisson law. For example, with increasing frequency Periodically pulses most of the time on the forward output RS-flip-flop 109 (Figure 5)

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there is a logical O, which leads to a decrease in voltage at the output of the integrator 110, i.e. a decrease in the threshold voltage at the second input of the comparator FROM and, consequently, an increase in the frequency of occurrence of pulses at its output. This process occurs until the average frequency of the pulses at the output of the oscillator 47 of the generator 47 is comparable with the frequency of the periodic pulses.

A further increase in the frequency of statistical pulses is impossible, since this would lead to a longer occurrence of logical 1 at the direct output of the RS flip-flop 109, a corresponding increase in voltage at the output of the software integrator and a decrease in the frequency of the appearance of pulses at the output of the comparator 113 i.e. negative frequency feedback is performed.

Measurement mode of integral non linearity.

In this mode, the generator produces pulses with amplitudes increasing by a fixed, predetermined amount.

30 In this mode of operation, the switch 92 in the control unit 19 is set to the Measurement position (FIG. 4), the switch 93 is set to the Integral position (lower in FIG. 4),

,, switch 94 - to the Off position, switch 106 - to the Reset position (lower in Fig. 4) „At the output 23 of the block 19, a logical O is set, which sets the RS-trigger 40 to the O 11 and prevents the passage of pulses from the output 4 blocks 2 through the element AND 5. Logic O from output 26 sets O to D-trng45 ger 25, Logical O at output 21 prohibits the passage of pulses from output 7 of block 2 to the output of element I 9, while the contacts of relay 2 still close the output of the DAC 16 with the input of the transformer 53. Logic 1 at output 18 allows the walking pulses through elements IZ, 17 and 20, but prohibits entry by the inverse pulses through the passage denie element IW

55 A logical O at output 27 sets to O via the OR element 28 D-flip-flop 35 and through the OR element 29 a binary counter 15 and a binary-decimal counter 41,

When installing switch 106 in block 19, the start position (figure 4) at output 27 is set to logical 1, and binary counter 15 starts counting pulses arriving at its clock input through AND 3 and OR 14 from the output of clock generator 2, D measuring the integral nonlinearity of spectrometric units over the entire range of their input voltages, it is sufficient to form pulses with approximately thirty different amplitudes. Receiving more different amplitudes increases

time

a smaller number

amplitudes reduce the measurement accuracy of the integral nonlinearity. Using the CLP 16 at 4096 levels 02 bits) to obtain 32 different amplitudes, it is necessary to accumulate in a binary counter: 15 through 128 pulses. With the arrival of the 128th pulse at the output of the seventh bit of the dual counter 15, an impulse appears that, having passed through the element 17, sets the D-flip-flop 35 to one, Logic O on the inverse of the D-flip-flop 35 prohibits the passage of pulses the output of the clock generator 1 through the element And 3 on the clock input of the binary counter 15, This same pulse from the output of the element And 17, passed through the element OR 34, element 36, element OR 3 and the switch 48, is fed to the inputs of the imaging unit 49 of the pulse duration and one-shot 50 For certain STI believe that formirztots spectrometric pulses, then the output unit 51 switches the formers 49 and the pulse duration of the pulse at the output of the operational amplifier 54 is formed spectrometric pulse with an amplitude proportional to the voltage at the output of DAC 16.

The pulse from the output of the element 36 passes through the element 38, the delay of which is equal to the pulse duration at the output of the operational amplifier 54, through the element 20 and the element OR 28 and resets the D-flip-flop 35 to zero. Logic 1 at its inverse output permits the passage of pulses Bbrxofta clock generator i through the element And 3 on the clock input of the binary counter 15, K kodu corresponding to the counted per0

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A pulse of 128 pulses is added to the pulses until the output of the binary counter 15 has a pulse, indicating that another 128 pulses have been counted. The further process of forming a spectrometric signal with an amplitude proportional to the newly set voltage at the output of the DAC 16 is similar to that described.

If a 12-bit DPC 16 is used, binary counter 15 must also be 12-bit, therefore, having counted 4096 pulses, it is set to O, and the format of the next spectrometric pulses starts with the smallest amplitude. 4000 pulses counted by binary counter 5 correspond to the amplitude of the spectrometric signal equal to 10 V, then the amplitude increment step is equal to 0.32 V, therefore the minimum amplitude of the pulse generated in this 5 mode is equal to 0.32 V and with a step of 0.32 V increases to the maximum value of 10.24 V.

Differential nonlinearity measurement mode

D.T1I measuring the differential nonlinearity of the spectrometric units of the generator must produce pulses with an amplitude that varies linearly with time,

In this mode of operation, the switch 92 in the block 19 is set to the Measurement position, the switch 93 is set to the Differential position, the switches of the Spruce 94 are set to the Off position (figure 4), the other switches of the block 19 are in an arbitrary position. Then logical 1 at output 21 of block I9 permits the passage of pulses from output 7 of block 2 through element 9, and also triggers relay 22 and connects generator 52 output to converter 53. Logic O at output 18 of block 19 prohibits the passage of pulses through elements FROM, 17 and 20,

The generator 52 generates a linearly varying voltage with a maximum amplitude of 10 V and a rate of change of the order OdV / s, which is converted into a linearly varying current by the voltage-current converter 53. The formation of a pulley of esov at the output of the operational amplifier 54 is similar to that described in the second mode. Launch

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the formation is carried out by pulses from the output 7 of block 2 through the elements AND 9 and OR 37.

The mode of generating paired pulses.

This mode of operation is used for. checks of the operation of superimposed pulses, while the generator detects a pair of pulses with the possibility of Q adjusting the delay time of the second pulse relative to the first.

First, it is necessary to set the amplitude of the spectrometric or rectangular pulses. Then, the switch 94 in block 19 is set to the On position (lower in FIG. 4). Logical 1 from output 30 enters the control input of element 31 and permits its operation, as a result, pulses from the output of element AND 8 and delayed by element 31 are passed to the output of element OR 37. second modes

The firing of the pulse amplitude setting in the proposed generator is 0.024% when using a 12-bit GEL, which is approximately 8 times less than the error of the amplitude setting in the known (0.2%),

Expansion of functionality is achieved through the introduction of new modes of operation: the generation of pulses with a linearly varying amplitude, the generation of pulses with an amplitude varying with a certain increment, the generation of square impulses, the generation of pair pulses,

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Claims (3)

Invention Formula 1, Spectrometer pulse generator, containing, clock pulse generator, pulse shaper, switch, current switch block, the output of which is connected to the input of the operational amplifier and the first high-capacitor output of the operational amplifier is connected through the wave shaper and the buffer amplifier to the device output, the first the OR element, the NAND element, the differential pulse frequency meter unit, the output of which is connected to the control input No noise generator, the output of which is connected to the primary input of a differential pulse frequency meter unit, characterized in that, in order to improve the accuracy of setting the amplitude of pulses and expand the functionality of the device, the first to seventh elements were entered into it And, the pulse frequency divider block, block control, second through fifth elements OR, RS trigger, first, second, and third D triggers, first through fourth delay elements, first and second pulse shaping units, binary pulse counter in, the binary coded decimal pulse counter, a register, decoder, display unit, a comparator, a source 0 adjustable reference voltage, voltage converter - current, linear voltage generator, digital-to-analog converter, first and second relays, one-shot, 5 potentiometer, resistor, with the output of the clock pulse generator connected to the clock input of the pulse frequency divider unit and the first input of the first element I, the first output of the pulse frequency divider unit; connected to the first input of the second element And the clock input of the first: B-trigger, the second the output of the pulse frequency divider unit is connected to The first inputs of the third and fourth elements are And, the third output of the block is del- pulse frequency telephones are connected to the first input of the fifth element AND, the fourth output of the frequency divider unit 0 pulses are connected to the first input of the NAND element, and the outputs of the first and second elements AND are connected to the inputs of the first OR element, the output of which is connected to the clock input 5 binary pulse counter, the outputs of which are connected bit by bit with the inputs of the digital-output converter, the output of one of the bits of the binary pulse counter is connected to the first input of the sixth element I; The first output of the control unit is connected to the second input of the first element And, the inverse input of the third element And, the second input of the sixth element And, and the first input of the seventh element And, the second output of the control unit is connected to the second input of the fourth and v elements of And, and the control input of the first relay, third output block up0 five is connected to the second input of the second element And the second input of the fifth element And, the quarter output of the control unit is connected to the information input of the second D-flip-flop, the reset input of which is connected to the fifth output of the control unit, the sixth output of which is connected to the first inputs of the second and third elements OR, the seventh output of the control unit is connected to the control input of the first delay element, the eighth output of the control unit is connected to the control input of the second relay, the output of the second element I is connected to the first input four OR, whose second input is connected to the output of the sixth element AND and the clock input of the third D-flip-flop, and the output through the second delay element is connected to the first input of the fifth OR element, which is connected to the second input of the seventh AND element whose output is connected to the second input of the second element OR whose output is connected to the reset input of the third D-flip-flop, the inverse output of which is connected to the third input of the first element I, while the direct output of the second D-flip-flop is connected to the second input th third AND, vkod which is connected to the second input of the OR gate it dry, with the second input of the differential block meter pulse frequency, and 1 through the first delay element with the third input of the fifth OR element, the fourth input of which is connected to the fourth element AND, the inverse output of the second D-flip-flop is connected to the third input of the second And element, the input of the D / I converter and the third input of the fifth element And, the output which is connected to the reset inputs of the RS flip-flop, the first D-flip-flop and the second input of the third OR element, the output of which is connected to the reset inputs of the binary pulse counter and the binary-ten pulse counter, the outputs of which Erez serially coupled register and a decoder connected bitwise with the inputs of the indication unit, the output of DAC is connected to the NC and the generator output linearly varying voltage - with movable contacts of the first relay, surfing 18 five five Q 0 five 0 five five the main contact of which is connected to the input of the voltage converter — the current, the output of which is connected to the input of the current switch block; the output of the operational amplifier is connected to the disconnecting contact of the first contact group of the second relay and the first input of the comparator, the second input of which is and the output through the first pulse shaping unit is connected to the setup input of the RS flip-flop, the direct output of which through the second pulse shaping unit is connected to the clock input of the second D-flip-flop inverse of the RS-flip-flop output is connected to the fourth input of the second element AND and the information input of the first D-flip-flop, the direct output of which is connected to the second input of the NAND element, the output of which is connected to the clock input of the binary-to-pulse pulse counter and inverse (Lj vbh; od the first D-flip-flop through the fourth delay element connected to the register entry input, the output of the fifth element OR connected to the first, and the output of the noise generator - to the second contact switch p whose switching contact The output of the pulse width generator is connected to the break contact, and the one-vibrator output is connected to the closing contact of the second group of contacts of the second relay, the switching contact of which is connected to the control input of the current key block, while the potentiometer is connected parallel to the capacitor, the second output of which is connected to the opening contact of the first contact group of the second relay, the short-circuit contact of which is connected to the first output of the resistor, the second A output of which is connected to the input of the operational amplifier, informatsionnsh input of the third D-TpHi ger connected to a voltage source logical unit, and a non-inverting input of the operational amplifier is connected to a common bus, . 2. The generator according to claim 1, characterized in that the pulse frequency divider block comprises from the first to the seventh pulse frequency dividers, the first to the sixth And elements, the first to the seventh rezis191 tori, multi-position switch element OR, first to fourth pulse formers, with the first, second, third, fourth, fifth and sixth frequency dividers connected in series, and the output of the sixth frequency divider is connected to the third output of the block through the first pulse former, the frequency divider is connected to the first output of the block through the second pulse shaper, the first frequency divider is selected via the seventh frequency divider, and the third pulse shaper is connected to the fourth output of the block the input of the first frequency divider is connected to the clock input of the unit and the first input of the first element I, the outputs of the first, second, third, fourth and fifth dividers are connected to the first inputs of the second, third, fourth, fifth and sixth elements respectively, the outputs of which as well as the output of the first element I are connected to the corresponding inputs of the element. OR, the output of which through the fourth pulse shaper is connected to the second output of the block, the second input of each element I is connected to the corresponding contact of the multiple position nnogo switch, as well as through a corresponding resistor to the common bus, the set gopozitsionnogo central contact of the switch through the seventh resistor connected to the voltage source, 3. The generator according to claim 1, characterized in that the control unit contains first to sixth switches, first to third resistors, first and second integrators, first and second AND-NOT elements, first to third elements AND, first and the second elements are NOT, and the first contacts of the first, second, third and fourth switches through the first resistor are connected to 256712 ° with the bus voltage source, their second contacts are connected to the common bus, the switching contact of the first switch is connected to the first input of the first NAND element, the second input of which is connected to the switching contact of the second switch, the input of the first element NOT, the first 10 input of the first element and the third the output of the control unit, the output of the first IS element is connected to the second input of the first element AND and the fourth: output of the control unit, the third input of the first element I is connected to the output of the first integrating circuit, the input of which is connected to the voltage source bus, output the first element And is connected to the fifth output 2Q control unit, the first input of the second element is NOT connected to the switching contact of the third switch, and the second input is connected to the output of the first element NOT and the first input 25 of the second element AND, whose output is connected to the second output of the control unit, the output of the second element AND- NOT connected to the second input of the second element AND and through the second element NOT 30 first output control unit the switch of the fourth switch is connected to the seventh output of the control unit; the switch contact of the fifth switch is connected to the voltage source through the second resistor and the first contact is connected to the eighth output of the control unit; the first input of the third element is And is connected to the first contact 4Q of the sixth switch and through the third resistor with the voltage source bus, the second input of the third element I is connected to the output of the second integrating circuit, the input of which is connected to “With the voltage source bus, and the output of the third element I is connected to the sixth output of the control unit, the switching contact of the sixth switch- body is connected to the common bus. 35 w "IS Sh ., f. FIG. 2 Fig.Z f t / OChS-SG shz  Ö7 about nV, I / TUGA CfjffOC li t -IIJ 12 105 27 FIG. fl.7.5 35 / VflA5 | W 4h L ffw VNII1SH Order 3123/54 Circulation 901 Random polygons pr-tie, Uzhgorod, st. Project, 4 Subscription