SU1316075A1 - Controlled generator - Google Patents

Abstract

The invention can be used in radio-electronic devices, for example, in devices with phase auto-tuning frequency. The purpose of the invention is to simplify the device and increase the stability of its frequency. The controlled oscillator contains inverters 1-4 transistor 9, resistors 6, 10, and 11. As the inverters 1 and 2, an EXCLUSIVE OR element can be used, included as a non-inverting element. The proposed connection of the inverter 4 and the use of the NAND element as an inverter 3 eliminates the negative effect of the recharging process of the capacitor 5 On the passage of the avalanche-like recharging process of the capacitor 7. 3 Il. SO About O SP (Ru. /

Description

113

The invention relates to a pulsed technique and can be used in electronic devices, such as devices with phase locked loop.

The purpose of the invention is to simplify the device and to increase the stability of frequency ei o.

The goal is achieved by the fact that the output of the fourth inverter is connected to the second input of the third inverter, for which the AND-NOT element is used.

FIG. 1 shows the electrical circuit of the controlled generator; Fig. 2 shows potential variation diagrams at the input of inverter 4; in fig. 3 - time diagrams of potential changes.

The controlled pulse generator contains inverters 1 and 2 connected in series and logic element 2И-НЕ 3, inverter 4, the output of which is connected to the second input of element 2И-НЕ 3, capacitor 5 connected between the output of inverter 2 and input of inverter 1, resistor 6, included between the input of the inverter 1 and the output of the element 2I-HE 3 connected through a capacitor 7 to the cathode of the diode 8, the anode of which is connected to the common bus, on the base of the transistor 9, the emitter of which is connected to the input of the inverter 4 and through the resistor 10 to the common bus, and the collector is connected via re hist bus 11 from the source control voltage. I

FIG. 3 also indicates the potential and, at the input of inverter 1, the potential Uj at the output of inverter 2, the potential Uj at the output of element 2И-НЕ 3, the potential U at the input of inverter 4, the potential U at the output of inverter 4.

The controlled generator operates as follows.

Let initially at the input of inverter 1 and the output of inverters 2 and 4 a level of logic 1 is set, at the output of element 2I-NO 3 - logical O. At time t (FIG. 3, b), the discharge of capacitor 5 begins, with the result that Inverter 1 at time tj, the potential drops to level E (Fig. 3, U,), respectively, the state of inverter 2 (Fig. 3, Uj) and element 2I-NOT 3 changes. At the output of element 2I-NOT 3 At time tj appears high

ten

15

20

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1f U7j2

The cue potential (Fig. 3, Uj), which is through the capacitor 7 and the transistor 9 is fed to the input of the inverter 4 (Fig. 3, I), is low potential from the output of the latter, the potential fixes the state of the element 3 with high potential at its output. As the charge dg of the capacitor 7 is charged, the potential at the input of inverter 4 drops (Fig. 3, and) and reaches the response threshold at time t, an avalanche-like process occurs in the positive feedback loop along the circuit: output of inverter 4, second input of element 3, output element 2I – HE 3, capacitor 7, transistor 9, the input of inverter 4, which results in a low potential at the output of element 3 and the capacitor 7 discharges through diode 8 and the output of element 3, By the time an avalanche-like process starts at the output of inverter 2 and at first 3 the input element is set high potential, since the time constant of the capacitor 5 is many times smaller than the capacitor 7 P11STOYANNOY time.

At time U (Fig. 3,

Ii.

the discharge of the capacitor 5 begins, the potential at the input of the inverter 1 at the moment

five

0

five

0 time t falls to level E (fig. 3, and,),

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and at the output of element 2I-HE 3, a high potential is established at time tj and the processes are repeated. At the same time on the site tj, tj and t. , t recovers the charge of the capacitor 5.

The principle of oscillator frequency control is considered using the plot shown in FIG. 2, where E, is the control voltage potential; E & D is the trigger threshold of the inverter 4; t, is the settling time at the input of the high potential inverter 4.

Curve I is the change in potential at the input of inverter 4 for the case when E, G1 Ey, where is the amplitude of the pulse at the output of inverter 3.

50

Curve II fits the occasion.

when Е „, п

E

7 E

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55

The maximum value of the charge time of the capacitor 7 and, accordingly, the minimum value of the generator frequency occur in the first case.

The second case is characterized by the presence of two sections on the diagram of the input potential of the inverter 4.

313

The plot is characterized by a fast charge of the capacitor 7, when both transitions of the transistor 9 are shifted in the forward direction and the charge of the capacitor occurs through parallel-connected resistors 10 and 11,

Plot

H: characterized by the fact that the transistor 9 is already included as an emitter follower and, accordingly, the charge of the capacitor 7 occurs through its large input resistance.

In the third case, E E

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corresponds to the minimum value of the charge time of the capacitor 7 and, accordingly, the maximum value of the generator frequency. In this case, both transitions of the transistor remain displaced in the forward direction during the entire period of formation of pulses at the output of the inverter 4.

Instead of two inverters 1 and 2, an EXCLUSIVE OR element may be used, included as a non-inverting element, i.e. one entrance is connected to the common bus. The principle of operation and stress diagrams remain the same, decreasing. The number of connections and elements in the structural diagram.

The invention, in comparison with the known-30 additional input of the third inverting device, allows to eliminate

the negative impact of the re process

Spare additional capacitor 5 on the passage of the avalanche process of recharging capacitor 7, which increases the frequency stability. At the same time, diode 8 becomes unnecessary, which simplifies the generator circuit.

to / about ts

20

25

Claims (1)

Invention Formula A controlled generator containing three inverters connected in series, the first capacitor connected between the output of the second and the input of the first inverter, a resistor connected between the input of the first inverter and the output of the third inverter connected through the second capacitor to the cathode of the diode, the anode of which is connected to the common bus, and the base of the transistor, the emitter of which is connected to the input of the fourth inverter and through a common bus resistor, and the collector is connected via a resistor with a control voltage source bus different By the fact that, in order to simplify the device and increase the frequency stability, the output of the fourth inverter is connected to the second dotor, as the AND-NOT cop. which took ele and to t3 t IE FIG 2 t you h tl t2 J P Enop T-G 1 | Zt 1 ly tit 5 i Out 3 t Fig 3