SU1315995A1 - Logic processor - Google Patents

Abstract

The invention relates to the field of digital computing and can be used for the machine implementation of algorithms for processing odd information. The aim of the invention is to extend the functionality of the processor by ensuring that it implements the algorithms of the class state of the object — intermediate variable — solution. For this purpose, the processor contains a counter 2 intermediate parameters, two demultiplexers 22, .23, groups of ele (L with SP, SO with SP

Description

1315995

And 24-27, group of elements OR third multiplexer 32, and control - 28, 29, group of elements NOT 30, block trigger 33. 8 ill, 3 tabL. 31 comparisons of odd parameters

one

The invention relates to digital advanced technology and can be used for machine implementation of fuzzy information processing algorithms.

The purpose of the invention is to expand the functionality of the processor by ensuring that it implements the class algorithms, the state of the object — intermediate variable — solution.

Figure 1 shows the functional diagram of the logical processor; . Fig. 2 is a functional block diagram of the control unit; FIG. 3 is a functional block diagram of a comparison of fuzzy parameters; 4 shows an example of implementation of a comparison logic; figure 5 is a functional diagram of the operating unit; Fig. 6 is a functional diagram of a controlled trigger; Fig. 7 is a block diagram of the operation of the control unit; Fig. 8 is a timing diagram of the operation of the control unit.

The logic processor (Fig. 1) contains two multiplexers 1 and 2, a counter of 3 input parameters, a register 4 of input parameters, two blocks 5 and 6 of memory, three registers 7-9 of the number, a logic circuit 10 of comparison, a register 11 of the comparison code, a buffer register 1 2, two groups, elements OR 13 and 14, three groups of elements AND 15-17, operational unit 18, output register 19, control unit 20, intermediate parameter counter 21, two demultiplexers 22 and 23, fourth, fifth, sixth and the seventh group of elements And 24-27, the third and fourth groups of elements OR 28 and 29, a group of 30 elements NOT, a fuzzy parameter comparison block 31, a third multiplexer 32, and a controlled trigger 33.

The logical processor has information input 34, clock input 35,

36 output, start input 37. Control unit 20 (FIG. 2) contains a counter 38, a decoder 39, eight elements OR 40-47, nine elements AND 48-56,

two elements are HE 57 and 58 and a trigger 59. The control unit 20 has a clock input 60, an input 6 for the presence of input parameters, an input 62 for the presence of intermediate parameters,

starting input 63 and from the first to the fifteenth exits 64-78.

Block 31 comparison of fuzzy parameters (FIG. 3) contains comparison circuits 79, elements of the first 80 and

the second 81 groups and the element OR 82, Block 31 has two inputs 83 and 84 and output 85.

A comparison logic 10 (FIG. 4) can be built on the basis of a known device. Logit eska comparison circuit 10 contains commutation; tori 85, adders 87 modulo two, elements OR 88j elements AND 89, elements NOT 90 and has an input 91 and an output 92.

As the operation unit 18, a known operation unit may be used, which contains

(Fig.5) elements NOT 93, input elements OR 94, input elements AND 95, output elements OR 96 and output elements AND 97.

Operational unit 18 has the first

98 and second 99 information inputs, control input 100 and output 101,

The control / trigger 33 is built on the traditional scheme (FIG. 6) and contains the trigger 102, the element NOT 103, the element element AND 104 and 1 O5 and two elements OR 106 and 107, the Controllable trigger 33 has information input 108, First 109 and second software managers

moves and exit 111.

The logical processor functions as follows.

Operation starts at the Start signal, which arrives at the processor start input 37. At the same time, according to the clock signals arriving at the clock

The output of the comparison logic 10 is given a unitary code, the unit of which corresponds to the maximum element of the fuzzy set, In this

input 60 of control unit 20, it is at the same time as the signal from the eleventh

Finds a sequence of control signals. In the initial state at all outputs, the control unit 20 is set to passive levels.

The first memory block 5 has a page organization, with each page corresponding to a single input parameter, and each cell to a specific value of the input parameter. .

In the first cycle, the signal from the first output of the control unit 20, which arrives at the setup input of the account. In the third cycle, the signal from the second output of the control unit 20 implements the deduction of one unit from the content counter 3 input parameters, which means a transition to the next parameter. In this case, the contents of the counter 3 addresses the next page of the first memory block 5 and connects to the input of register 4 the next input of the first multiplexer 1, to which

Chika 3 input parameters, this account-20 is given the value of the corresponding

The chip is reset, corresponding to the first parameter being analyzed. The operation of counter 3 is illustrated by the table of truth.

The information inputs of the counter are supplied with a constant code equal to the number N of input parameters. Table 1 describes the operation of the counter 21 intermediate parameters.

The information from the output of the counter 3 input parameters goes to the first address input of the first memory block 5, selects a page, and also controls the input of the first multiplexer 1, allowing the input parameters of the register 4 input parameters to the value of the corresponding parameter. In the same cycle, the signal from the tenth output of the control unit 20 is realized. is to write the current value of the parameter to the register A of the input parameters.

In the second cycle, the signal from the third output of the control unit 20 incoming to the read input of the first memory block 5 and the synchronization input of the first register 7 of the number reads the information from the first memory block 5 to the first register of the 7 number. The read information is a fuzzy set — a vector of degrees of belonging of the input value to the linguistic term values of the input variable. The elements of this vector are compared with each other by comparison logic 10, which exceeds the maximum of them.

The output of the comparison logic 10 is given a unitary code, the unit of which corresponds to the maximum element of the fuzzy set, In this

same clock signal from the eleventh

the output of the control unit 20, the code from the output of the comparison logic 10 is loaded into the comparison code register 11.

In the third cycle, according to the signal from the second output of control unit 20, the unit is subtracted from the contents of the counter 3 input parameters, which means a transition to the next parameter. The content of counter 3 addresses the next page of the first memory block 5 and connects to the input of register 4 the next input of the first multiplexer 1, to which

the value of the corresponding is given

input parameter. On a signal at the tenth output of control unit 20, this value is entered into a register of 4 input parameters.

0

e

In the fourth clock cycle, the signal from the third output of the control unit 20 is used to match the corresponding fuzzy vector from the first memory block 5 to the first register of the 7th number.

In the fifth cycle, the control unit 20 outputs the following signals: a signal at the fifth output, arriving at the control, the south input of the operation unit 18; the signal at the sixth output, arriving at the second outputs of the first 15 and second 16 groups of elements And; signal at the seventh output to the second input

0 of the third group of elements And 17, In this case, the information from the output of the first register of the 7th number through the first group of elements I I5 and the first group of elements OR 13 goes to the first input

5 operational unit 18. The second input of operational unit 18 through the second group of elements AND 16 and the third group of elements OR 28 receives information from the output of the buffer register 12. The words in the first register are 7 numbers and the buffer register 12 have the same format and are divided into N fields, each of which contains the code of the degree of belonging of the input value to a fuzzy set. Operational unit 18 implements a pair-wise comparison of the contents of the fields applied to its inputs, and outputs a unit to the corresponding output in the case when the value 513

the first input is strictly less than the second, the N-bit code is compared with the output of the operation unit 18 through the second group of elements OR 14 and the third group of elements AND 17 is fed to the synchronous input of the buffer register 12, each bit of the N-variable the synchronous input of the buffer register 12 controls the reception of information in the corresponding field, so that the field of the buffer register 12 is synchronized separately, since the information input of the buffer register 12 is connected to the output of the first register of the 7th number, as a result The minimum values of the contents of the corresponding fields of the first register of the 7th number and the buffer register 12 are stupid. When starting the processor into operation, buffer-register 12 must be filled with units. In the same clock cycle, by a signal from the sixth step of the control unit 20, the counter 21 of intermediate parameters is set to the initial state.

In the sixth cycle, the signal from the thirteenth output of the control unit 20 arriving at the first control input of the controlled trigger 33, is set. At the same time, the information input of the trigger 33 via the third multiplexer 32 receives the contents of the bit register of the 19th output, the number of which is determined by the contents of the counter 21 of intermediate parameters. The first control input of the controlled trigger 33 is the enrollment input, therefore the trigger 33 is set according to the value supplied to its information input. The operation of the controlled trigger 33. is described in Table 2 (X is an idle state).

In the same clock cycle, the signal from the fourth output of the control unit 20, which enters the read input of the second memory block 6 and synchronizes the second register of the 8th number, compares the value of the intermediate parameter from the second memory block 6 to the second register of the 8th number. This value is generally fuzzy, i.e., represents the vector of the degree to which the parameter belongs to different classes. The format of the word in the second register of the 8th is similar

five . 6

Formats in the first case of 7 numbers and buffer register 12.

In the seventh cycle, the control unit 20 generates a signal at the fifth output, arriving at the control of the 1st input of the operation unit 18, as well as a signal at the twelfth output, arriving at the second inputs of the fourth 24 and sixth 26 groups of elements And sync

input third register 9 numbers. In this case, the processor implements the following actions. The contents of the second register of the 8th number are posted to the first input of the seventh group of elements AND 27, as well as through the sixth group of elements AND 26. and the first group of elements OR 13 enters the first input of the operation unit 18. The content of the buffer register 12 defined by

the state of the intermediate parameter counter 21 is transmitted through the second multiplexer 2 to the information input of the first demultiplexer 22. The first demultiplexer 22 passes information from the input to one of its outputs in accordance with the code on register 11 of the comparison code. The remaining outputs of the demultiplexer 22 are set to zero. The operation of the first demultiplexer 22 is described in Table 3 of truth (X is the information at the input of the demultiplexer).

The meaning of the conversion implemented by the second multiplexer 2 and the first demultiplexer 22 is as follows. The information stored on buffer register 12 represents

is the vector of the degree of belonging of the input parameter to various intermediate parameters. The second multiplexer 2, controlled by the intermediate parameter counter 21, allocates

an element of the vector (the field of the buffer register 12) corresponding to the intermediate parameter processed in this cycle. The value of the intermediate parameter is generally fuzzy, i.e. it is a fuzzy subset of some set of classes. The class in which the intermediate parameter can be incremented is determined by the contents of the comparison code register 11. This register controls the passage of the value; ki on the corresponding to this class. the output of the first demultiplexer 22, With the output of the first demultiplexer 22

71

this information comes in the first input of the fifth group of elements AND 25, as well as through the fourth group of elements AND 24 and the third group of elements OR 28 to the second input of the operation unit 18. Thus, the operation unit 18 implements the E in this case elementwise comparison of the stroke fields on the second register 8 numbers and at the output of the first demultiplexer 22. The comparison code from the output of the operation unit 18 goes to the second input of the fifth group of elements I 25 and through the group of elements NOT 30 on the second entrance of the seventh group of elements And 27, P 25 and seventh 27 groups And lementov divided into subgroups (10), each of which corresponds to one field of the information word. At the same time, the second inputs of the AND elements of one subgroup are interconnected and connected to the corresponding bit of the second input of the AND group, since the output of the first demultiplexer 22 contains nonzero information only in a single field, then all the subgroups of the fifth group of AND elements 25, the corresponding other fields are blocked by zero signals from the output of the demultiplexer 22. According to the condition of operation of the operation unit 18, all its outputs corresponding to these fields are set to zero signals (input 1 & 2 ). These signals, with a group of elements of NOT 30, are sent to single values to the second inputs of the respective subgroups of the seventh group of elements And 27. Thus, the inputs of these fields of the third register, the 9th number, through the seventh group of elements And 27 and the fourth group of elements OR 29 receive information the corresponding fields of the second register are 8 numbers. For the field allocated by the register 11 of the comparison code, at the output of the first demultiplexer 22, its content is compared with the contents of the corresponding field of the second register

.ra 8 numbers. At the corresponding output of the operation unit 18, depending on the result of the comparison, a value is set which passes the information to the input of the specified third register 9 number or from the output of the first demultiplexer 22 through the fifth group of elements AND 25

958

the fourth group of elements Ш1И 29, or from the second register 8 numbers through the seventh group of elements AND 27 to the fourth group of elements OR 29. This value is the large of the compared ones. On a signal from the twelfth output of the control unit 20, the information is recorded on the third register on the 9th.

Thus, in the third register 9 of the number, a fuzzy value of the intermediate parameter is formed, corrected for the newly received value of the input parameter.

In the eighth clock cycle, the signal from the fifteenth output of the control unit 20, the value generated on the third register 9 of the number is recorded in the second memory block 6.

In the ninth clock cycle, the signal from the fourteenth output of the control unit 20, arriving at the second control input of the flip-flop 33, inverts its state (Table 2

instinnoti trigger 33). In the same cycle, the signal from the fourth output of the control unit 20 is used to derive the fuzzy value of the intermediate parameter from the second

memory block 6 to the second register 8

numbers

I.

In the tenth in block 31 comparison of fuzzy parameters,

comparison of fuzzy values of the parameters recorded in the second 8 th and third 9 number registers. A comparison of fuzzy values can be implemented as follows. Is considered

that the classes making up the base set of the fuzzy parameter are ordered. The degrees of the parameter belonging to the highest classes are compared. In the case of inequality, the result of their comparison is considered the result of comparison of fuzzy values. If the degrees of primordiality of the compared fuzzy sets are equal, then the affiliation to the next in order will be compared.

class and t, d. At the output of fuzzy parameter comparison block 31, a single value is set if the value of the fuzzy parameter at the second input is greater than the first one. The comparison result from the output of fuzzy parameter comparison block 31 through the second demultiplexer 23 is fed to the output register 19, the Demulti1lexer 23 is controlled by the code on the counter 21

91

intermediate parameters and provides a comparison result for the corresponding register register 19 of the year. At the same time, the remaining outputs of the demultiplexer 23 are set to zero. The signal from the eighth output of the control unit 20 is used to receive information on the reed register 19. The register 19 of the video recorder is implemented on T-triggers, as a result of which a single signal at the output of the fuzzy parameters comparison block 31 provides the inversion of the corresponding bit of the register 19 of the output. In the same clock cycle, by the signal from the eighth output of control unit 20, the unit is subtracted from the contents of the counter 21 intermediate parameters. The states of the counter 21 of the intermediate parameters and the counter 3 of the input parameters are analyzed by the control unit 20. If the contents of the counter 21 of the intermediate parameters are not zero, then the transition to the sixth cycle is performed, followed by the correction of the next intermediate parameter and the corresponding decision. When the contents of the counter 21 of the intermediate parameters are equal to zero, the transition to the eleventh cycle is performed.

In the eleventh cycle, signals from the seventh and ninth outputs of the control unit 20 are fed to the synchronization input of the buffer register 12, and as a result, information from the first 7th register is entered into this register. In the same cycle, the state of the counter 3 is analyzed in a single parameter; If its contents are not zero, then go to the third clock cycle to enter and process the next input parameter. When the contents of the counter 3 of the input parameters are equal to zero, the processor operation cycle ends and the control unit 20 returns to the initial state of waiting for the start signal. On the register 19 vyshod. Formed the output solution.

The proposed device is a specialized process accordingly to the installation trash. As a basic variant of the counting and counting inputs of the input counter, serial micro-parameters can be considered, the output of which is connected to the Electronics-60 computer. Compared to the second address input of the first with the base object, the proposed memory unit, to the address input of the first 5995

ten

This feature significantly reduces the implementation time of the algorithms.

For the values,,,, where N is the number of input parameters, M 5 is the number of intermediate parameters, P is the number of frequency classes, the following algorithm implementation times are obtained. For the base object t 1400 ISS, for the proposed device

 About you ts 90 ISS.

15

Thus, the speed will be 15 times.

Claims (3)

Invention Formula 0 0 0 1; A logical processor containing two multiplexers, an input parameters counter, an input parameters register, two memory blocks, three number registers, a comparison logic, a comparison code register, a buffer register, two groups of OR elements, three AND groups, an operational block, 5 an output register and a control unit, the information input of the processor is connected to the information input of the first multiplexer, the output of which is connected to the information input of the register of input parameters, the output of which is connected to the first address input of the first memory block, the output of which is connected to the information input of the first register of the number, the outputs of which are connected to the first inputs of the elements AND of the first group, the outputs of which are connected to the first inputs of the elements of RSHI of the first group, the output of the comparison logic circuit n to the information input of the comparison code register, the outputs of the operation unit are connected to the first inputs of the elements OR of the second group, the outputs of which are connected to the first inputs of the elements AND the second group, the outputs of which are connected to the synchronous inputs of the buffer register, the outputs of which are connected to the first inputs of the elements AND the third group , the output of the second memory block is connected to the information input of the second number register, the processor clock input is connected to the clock input of the control unit, the first and second outputs of which are connected the first multiplexer and the input of the presence of the input parameters of the control unit, the third output of which is connected to the read input of the first memory block and the synchronous input of the first number register, the fourth output of the control unit is connected to the read input of the second memory block and the synchronous input of the second number register, fifth, sixth , the seventh, eighth and ninth outputs of the control unit are connected respectively to the control input of the operation unit, the second inputs of the elements AND, the second group of elements AND, the second inputs of the third group, the synchronous input p Giustra vshoda and second inputs of the OR elements of the second group, vshoda register output is connected to the processor output, distinguishing with the fact that, in order to expand the functional capabilities of the processor by allowing the implementation of the class of algorithms they state of the object - the intermediate variable - a solution, in which t we have an intermediate parameter counter, two demultiplexers, from the fourth to the seventh groups of AND elements, the third and fourth groups of OR elements, NOT elements, a fuzzy parameter comparison unit, a third multiplexer and a trigger, the output of the first number register connected to the input of the comparison logic circuit and the information input of the buffer register, output which is connected to the information input of the second multiplexer, the output of which is connected to the information input of the first demultiplexer, whose address input is connected to the output of the comparison code register, the output of The plexor demo is connected to the first inputs of elements of the fourth and fifth groups, the outputs of elements of the fourth group are connected to the second inputs of the elements OR of the third group, the first inputs and outputs of which are connected respectively to the outputs of the elements of the second group and the second information inputs of the operation unit, output the intermediate parameter counter is connected to the address input of the second multiplexer and the first address input of the second memory block, the output of which is connected to the information input of the second register of numbers a, the outputs of which are connected to the first inputs of the block of comparison of fuzzy parameters and elements of the sixth and seventh groups, and the outputs of the elements of the sixth group are connected to the second inputs of the elements OR of the first group, the outputs of which are connected to the first information inputs of the operating unit, the outputs of which are connected to the second inputs of the elements of the fifth group and through a group of elements NOT to the second inputs of elements AND the seventh group, the outputs of the elements of the And the fifth and seventh groups are connected respectively to the first and second inputs of the elements OR the fourth group, the outputs of which are connected to the information inputs of the third register of the number, the output of which is connected to the information input of the second memory block and the second input. a fuzzy parameter comparison unit, the output of which is connected to the information input of the third multiplexer; the output of which is connected to the information input of the trigger, the output of which is connected to the second address input of the second memory block, the address inputs of the second demultiplexer and the third multiplexer are connected to the output of the counter intermediate steam meters, the installation input of which connected to the second inputs of the elements of the first group and the sixth output of the control unit, the eighth output of which is connected to the counting input of the intermediate parameters counter, the output of which is connected to the input of the indication of the intermediate parameters of the control unit, the tenth and eleventh outputs of which are connected to synchronous inputs, respectively, of the input parameters register and the comparison code register, the twelfth output of the control unit is connected to the second inputs of the AND elements of the fourth and sixth groups and the synchronous input of the third number register, thirteen, fourteenth and fifteenth outputs of the control unit are connected respectively to the first and second control inputs of the trigger and the recording input of the second memory block, the start input of the control unit is the same input of the processor. 2. The processor in accordance with claim 1, 1, and TL is that the control unit contains a counter, a decoder, eight OR elements, nine AND elements, two NOT elements and a trigger, with the first, second, third and even 131 The zero bits of the information output of the counter are connected to the corresponding bits of the decoder input J whose first output is connected to the first output of the control unit to the first input of the first OR element, the output of which is connected to the tenth output of the control unit, the second output of the decoder is connected to the first input of the second OR element and the eleventh output of the control unit; the third output of the decoder is connected to the second input of the first OR element and the second output of the control unit; the fourth output of the decoder is connected to the second the input of the second OR element, the output of which is connected to the third output of the control unit, the fifth terminal of the sub-decoder decoder is the sixth output of the control unit, the first input of the third OR element, and the second input of the fourth OR element, the output of which is connected to the fifth output of the control unit, the sixth output the decoder is connected to the thirds adatom of the output of the control unit, the second input of the fifth OR element, the output of which is connected to the fourth output of the control unit, the seventh output of the decoder, is connected to the first input of the fourth elec the OR or dual output of the control unit; the eighth output of the decoder is connected to the fifth output of the control unit; the ninth output of the decoder is connected to the fourteenth output of the control unit and the first input of the fifth OR element; the input of the first element And, the eleventh output of the decoder is connected to the ninth output of the control unit, the second input of the second element And, the second input of the third element And, the second input of the third element OR, the output of which It is connected to the seventh control unit code, the input bits of the sign of the presence of the input parameters of the control block are connected to the corresponding inputs of the sixth element OR, and the bits of the input of the sign are intermediate parameters of the block . control - to the corresponding inputs of the seventh element OR, the output of which is connected to the first input of the first element AND, the output of the sixth element OR is connected to the first 5995 14 the input of the third element And, the output of which is connected to the second input of the fourth element And, the output of the first element And connected to the first the input of the eighth element OR and the second input, the fifth element AND, the output of which is connected to the third section of the information input of the counter, the output of the second element AND is connected to the second input of the sixth element AND, the second input of the eighth element OR, the output of which is connected to the second input of the seventh element AND, and through the NOT element to the second input of the eighth element AND whose output is connected to the counter input of the counter, the second bit of the information input of the counter It is connected to the bus of the unit potential of the block, the first input of the fifth element I and the first input of the sixth element I, the output of which is connected to the first discharge of the information input of the counter, the fourth discharge of the information input of the counter bus block zero potential, an output of the fourth AND Con chen to inputs installation O counter and trigger direct input of which is connected to a first input of a ninth element And, the clock input of the control unit is connected to the second input of the ninth element And, the output of which is connected to the first input of the fourth element And, the first input of the eighth element And to the first input of the seventh element And, the output of which is connected to the synchronous input of the counter, the start input of the control unit is connected to the setup input of the trigger. 3. The processor according to claim 1, of which is a comparison of the fact that the comparison block of fuzzy parameters contains n comparison circuits (where n is the size of the fuzzy vector), i - 2 elements And the first groups (, п), i-1 elements AND of the second group, element OR, and the bits of the first and second blocks of comparison of fuzzy parameters connected to the first and second inputs of the respective 1x comparison circuits, the first output of the first comparison circuit is connected to the first input of the OR element, the second output of the first comparison circuit is connected to the second inputs of the first elements of the first and second groups, the first output of the i-th comparison circuit ( i 2, p) is connected to the first input of the (i-1) -th element AND 151315995 6 the second group, the second output of the i-th circuit and the second group, the output of the i-r element, we compare (i 2, p-1) is connected to and the second group is connected to (1 + 1) -th the input of the OR element, the output of which is the output of the comparison unit to the non-first input (i-l) -ro of the AND element the first group, the output of the i-ro element And the first group is connected to the second 5 clear parameters. inputs (1 + 1) -x elements And the first about o 1 1 oh oh X x 0 ... 01 0 ... 10 Table 1 table 2 about one X X o,; about 1 about 1 1 about Table 3 . about X oh oh X 10 ... About Continuation of table 3 85 srig.Z 9g 7 . , finnnnn ppp jn n m gp JTL Fig.d JTL Editor O. Bugir Compiled by N.Zaharevich Tehred i.Glushchenko Proofreader T. Kolb Order 2365/52 Circulation 672 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, ul. Project, 4