SU1311015A1 - Device for transmission of discrete signals - Google Patents

Abstract

The invention relates to a pulse technique, and can be used in digital devices, automation and computing. The purpose of the invention is to increase speed and increase the output level of a logical unit. The device contains a pnp transistor 1, resistors 3,9,10, 12, TTL-element 5, pn-p-transistor 8. To achieve this goal, a capacitor 6 is inserted into the device and an AND – NE element is used in TTL-element. 1 il. (L

Description

I1

The invention retracts to the digital technology and can be used in digital automation and numerical equipment devices.

The aim of the invention is to increase the speed of action and the increase in the Bi level of the logical unit.

The drawing shows a schematic diagram of a device for transmitting discrete signals,

The device for transmitting discrete signals contains a pn transistor emitter of which is connected to the output 2 of the device, and the base through the first resistor 3 is connected to input 4 of the device and the first input of the TTL element 5 H-HEj whose second input is connected to the collector n -p-p-transistor 1, whose base through a capacitor 6 is connected to a common bus 7, the base and emitter of a pnp-transistor 8, respectively, through the second and third resistors 9, 10 are connected to the power bus 1, the collector is connected to the output 2 devices, and the base through the fourth resistor 12 is connected to the output TTJ7 element 5

The device for the transmission of discrete signals works as follows

Let us assume that the input of 4 is a logical O (U ::: 0) level. Because TTL-element 5 inverts a logical signal, there is a high level at its output (U L-fSB due to resistors 9912). Therefore, at pn-transistor 8 is locked. At this time, the pn-transistor i is also locked, since there is a level of potential at its base. Therefore, at the output 2 of the device, i.e. on load - low potential level (U °% O), V

In this case, with the closure of the closure (short-circuit) of output 2 to the common bus 7 (short-circuit between the signal and screen conductors of the load cable or twisted pair) there is no danger of the pnp transistor 8 to be broken,

Suppose on input 4 is filed dropped; logical: escal I. Since at the input of the pn-p-transistor 1 there is an integrating circuit on the resistor (e 3 and cc dens.tor 6), the positive signal difference at the input 4 reaches the base of the pn-p-transistor 1 determined by the delay. During this time, the TTL-element 5 has time to work. As a result, the output of the TTL-element is

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low potential (). Therefore, the pn-transistor 8 is opened. At the output 2 of the circuit, a high potential level (U) is obtained, which maintains the locked state of the n + transistor 1.

In this state, if K 3 occurs, the output to the common bus 7, the pn-transistor 1 will open and the potential will be low at the second input of the TTL element. Consequently, the TTL element 5 is switched off, at its output the potential will increase and the pn-transistor 8 is closed. Thus, the breakdown of the pn-transistor 8 from the current k, h is prevented. During the response time of the feedback circuit (pn-p-transistor 1, TTL-element 5 on resistors 9, 12), the pn-p-transistor 8 is open and a short circuit current flows through it. During this time, so that the pnp transistor 8 does not break through, a limiting resistor 10 is placed on its coupling (or count, light) chain. When the short circuit is eliminated. Pr-p-transistor I is locked, the reverse switching of the TTL-element 5 occurs and the pnp-1-razistor 8 opens again.

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A device for transmitting discrete signals containing a pn-transistor, the emitter of which is connected to the output of the device, and the base is connected to the first output, one of the first resistor, P a-p-granzistor5 base and the emitter of which, respectively, through the second to the third resistors are connected to bus power, TTL-element5 the first input of which is connected to the input of the device to the output is connected to the first output of the fourth resistor, so that, in order to increase speed and increase the output level of the logical unit, a capacitor is inserted , as TTL element Hcnon j3OBaH IYE element;,. the first entrance of which is connected to the second well drive of the first resistor, the second input is connected to the collector of the pnp transistor, the base of which is connected via a common bus, Eensat (connected to the common bus, the second output of the quad resistor is connected to , the collector of which is connected to the output, and in the case of:

Claims (1)

FORMULA. inventions A device for transmitting discrete signals, containing a pnpn transistor, the emitter of which is connected to the output of the device, and the base is connected R. the first output of the first resistor, p-a-p-transistor., the base and emitter of which, respectively, through the second and third resistors are connected to the power bus, a TTL element, the first input of which is connected to the input of the device, and the output is connected to the first output of the fourth resistor, It is noteworthy that, in order to increase the speed and increase the output level of the logical unit, a capacitor is introduced, and an I-NOT element is used as a TTL element, the first input of which is connected to the second output of the first resistor , the second entrance - with collectively rum of a transistor, the base of which is connected via a capacitor to a common bus, the second terminal of the fourth resistor is connected to the base of a transistor, the collector of which is connected to the output of the transistor.