SU1310823A2 - Channel simulator - Google Patents

Description

1 1310823

The invention relates to computing and can be used to monitor and adjust peripheral devices.

The purpose of the invention is to reduce the time of peripheral devices (PU).

Figure 1 shows the block diagram of the simulator; FIGS. 2 and 3 are functional diagrams of a time counting unit and block counter 43, element OR 44, signal bus 45 Number of bytes of the information input of the block, bus 46 - 49 signals Reset of the control panel, status byte and control input of the block.

The restarting unit 11 contains (FIG. 9) the element OR 50, the elements AND 51 - 55, the generator 56 of the reference control hour; 4 is a graph-algorithm, frequency divider 57, switch 58, element OR 59, buses 60-64 signals, Frequency Code, Generator, Remote Reset, Complex and Bedurhythm of the control unit; Figures 5-10 are functional diagrams of a standard interface block, a data storage unit, a data generation unit, a selective indication unit, a restart unit, an operator console.

The simulator contains (Fig. 1) bus 1 information I / O, standard conjugate block 2, control block 3, buffer register 4, data memory block 5, control word block 6, data generation block 7, data register 8, register 9 control words, selective indication block 10, restart block 11, operator panel 12, tires 13 and 14 of the simulator reset input and output, and block 15 of time counting.

The time counting unit 15 includes (FIG. 2) a time stamp generator 16, a counter 17 and a comparison circuit 18.

Control unit 3 contains (Fig. 3) an input multiplexer 19, a fixed memory 20 and an output register 21.

Standard interface block 2 contains (FIG. 5) amplifiers-transmitters 2, amplifiers-receivers 23 of identification and control signals, amplifiers-receivers 24 of the BUS-A signal, amplifiers-transmitters 25 of the BUS signal, definition control unit 26, circuit 27 address comparisons, pilot pattern generation unit 28, descrambler 29 bytes of state, and switch 30.

Data memory block 5 contains (Fig.6) memory 31, switch 32 upper address bits, switch 33 lower address bits, comparison circuit 34, data counter 35, signal bus 36 Address block input operation.

Data generation unit 7 is inclusive

25

The first input block. t5 I

The console 12 of the operator contains (figure 10) the register 65 of the interface signals, the elements 56 of the display, toggle registers 67 - 70, switches 71 modes, buttons 72 reset and initial start.

Using bus 1, a channel simulator (IR) is connected to a peripheral device (PU). Unit 2 matching the input and output signals of the interface, complements the codes of addresses, operations and data transmitted to the control panel over the bus 1 (SHIN-K) with the check bit, compares the address received from the control panel over the bus 1 (BUS- A), with a given, controls for clarity the bytes of addresses, states and data received from the control panel over SN-A, decrypts the status byte.

The control unit 3 ensures the coordination of the operation of all IC nodes using control and synchronization signals generated by the block in Q in accordance with a given program, modes, signals from the control panel and operation algorithms.

Buffer register 4 is used for storing data bytes, addresses, with AND STATUS, received via SHIN-A from the control unit through block 2; the contents of the buffer register 4 is indicated on the operator's panel 12.

Data memory block 5 serves for storing and issuing to PU via SHIN-K through register 8 and data block 2 previously stored in block 5 from console 12. This data is mainly necessary for marking media, for 50

Data memory block 5 serves for storing and issuing to PU via SHIN-K through register 8 and data block 2 previously stored in block 5 from console 12. This data is mainly needed for media marking, as shown (FIG. 7) switch 37, register 38

a shift, a fixed memory 39 characters- 55 Dani borders and zones, etc. when working

codes, the counter 40 and the circuit 41 with PU type tape drives, compare.

The selective indication unit 10 has (FIG. 8) a comparison circuit 42.

kakh, drums (i.e., data organized in arbitrary rather complex structures).

counter 43, element OR 44, signal bus 45 Number of bytes of the information input of the block, bus 46 - 49 signals Reset of the console, Status Byte and Resolution of the control input of the block.

The restarting unit 11 contains (FIG. 9) the element OR 50, the elements AND 51 - 55, the frequency generator 56, the frequency divider 57, the switch 58, the element OR 59, the buses 60-64 signals, the frequency code, the generator, the console reset, the Complex and Bedu0

five

The first input block. 5 I

The console 12 of the operator contains (figure 10) the register 65 of the interface signals, the elements 56 of the display, toggle registers 67 - 70, switches 71 modes, buttons 72 reset and initial start.

Using bus 1, a channel simulator (IR) is connected to a peripheral device (PU). Unit 2 matching the input and output signals of the interface, complements the codes of addresses, operations and data transmitted to the control panel over the bus 1 (SHIN-K) with the check bit, compares the address received from the control panel over the bus 1 (BUS- A), with a given, controls for clarity the bytes of addresses, states and data received from the control panel over SN-A, decrypts the status byte.

The control unit 3 ensures the coordination of the operation of all IC nodes using control and synchronization signals generated by the block in Q in accordance with a given program, modes, signals from the control panel and operation algorithms.

Buffer register 4 is used to memorize data bytes, addresses with AND STATE, received via SHIN-A from the control unit through block 2; the contents of the buffer register 4 is indicated on the operator's panel 12.

Data memory block 5 is used for storing and issuing to PU via SHIN-K through register 8 and data block 2 previously stored in block 5 from console 12. These data are mainly needed for marking media, for

with PU like drives on tapes, disks, drums (ie, data organized into arbitrary rather complex structures).

3 13

A control word memory block 6 for storing a program specified from the console 12 consisting of control words whose format is shown below.

NPU KOP KChF PL BPD VZ I

where NPU is the field number of the peripheral device;

KOP - opcode field;

CC - the number of numbers field;

BDC — field of the memory database;

FL - checkbox field;

VZ - field delay time. The contents of the fields NPU and KOP in PU. The content of the CS field is determined by the number of data bytes transferred to the control panel or received from the control panel. The PL field contains checkboxes — signs of blocking the data count, the data chain and commands, and working with one type of data or another. It is intended to programmatically partition the data memory into zones by baseing the address. The content of the OT field determines the time delay between the end of one control word and the start of execution of the next control word.

Registers 8 and 9 are used to store the current values of the data byte and the control word, respectively. Writing to registers 8 and 9 is made from the corresponding block 5, 6 or console 12.

The selective indication unit 10 controls the writing to the buffer register 4 12 data bytes set from the console or states received from the control panel. The restarting unit 11 provides the cyclic operation mode of the IC in the presence of faults in the control panel, as well as the joint operation with other IRs and is connected to the buses 13 and 14, the Operator Console 12 is used to set the G operation modes and monitor the control panel operation.

The device works as follows.

Block 15 forms a time interval between the end of the execution of one control word and the start of execution of the next control word. The generator 16 serves to form time marks. The counter 17 records the time interval value after the end of the execution of the next control word. This one was08234

the rank is compared with the value specified in the control word (in the OT field) using the comparison circuit 8 with the subsequent generation of the signal going to block 3, depending on the result.

There are two types of work Programming and Control PU. Type of work Programming is intended for setting the program for testing the control panel and operating modes of the IC. The task of the program consists in writing to block 6 through the register 9 of control words set from the console 12, by addresses, for f5 data also from the console 12. In this case, the time delay between the end of the execution of one control word and start of execution of the next control word. If there is no need for a time delay in this field, zeros are written. If there are control words in the program containing a sign of work

5 with the memory, then from the console 12 through the register 8 in the block 5 the data is entered. In addition, on the remote control 12, the controls set the main and auxiliary modes.

0 Main modes: Tact, Automatic Generator, and auxiliary; Mono Pol, Slave, Complex, Selection Block included, etc.

g. After setting the verification program, it is monitored, and if necessary, the Data Control by sending control words and data to the display elements of the console 12, respectively, from blocks 6 and 5 through registers 9 and 8. in which the check itself is carried out. In this case, block 3

5 em from block 6 to register 9 first

control word and enters into the PU a sequence of signals of the initial sample, during which through block 2 the address bytes are received in the PU

0 and state. Unit 2 compares the address received from the control unit and specified in the control unit and analyzes the status byte. If the status byte does not contain a failure pointer, then block 3 organizes data exchange with the control panel. When data is received from the PU, the IR data is monitored by block 2 for clarity and, if necessary, (a clear error in the data mode of operation Tact is entered into the buffer register 4 and indicated on the remote control 12. When transmitted to the PU, the latter are received from block 7 or block 5. The choice of the data source determines the value of the corresponding bits in the FL field of the control word, which is currently in register 9. If the data source is block 7, then the FL field also contains a pointer defining data type. If the data source is block 5, then the data address is determined by taking into account the control word BPD.

20

25

thirty

In the ending sequence, G receives the final byte of the state from the control unit and, depending on the pointers in the control field, completes the check (there is no control word string indicator in the FL field), or immediately goes on to execute the next control word (the FL pointer is set in the FL field control words and in the OT field there are zeros), or it proceeds to the next control word after a time interval equal to the contents of the OT field (the FL field contains the pointer of the chain of control words and the contents of the VZ different from zero). In the subsequent case, after the completion of the execution of the current control word by block 3, a signal is triggered to start the timer, zeroing the counter 17. Signals from the generator 16 output to the counting input of the counter 17. When the counter 17 coincides with the delay interval value set by the OT field of the last control - Q, a word, at the output of the comparison circuit 1-8, a signal is generated about the end of the delay time interval. This signal is analyzed by block 3 after the signal. The timer starts. Moreover, if the control word of the control word contains zeros, then the signal at the output of the circuit 18 is formed immediately after the signal that tilts the counter 17, and the IR goes on to execute the next control word

When receiving dannaps from PU there is a need for their visual control. If the PU is not able to work in

IR in Tact mode provides setting and resetting each interface signal by pressing the button on the remote control 12, in Automatic mode by pressing the button on the remote control 12, the entire program or its part is executed (if the control panel malfunctions). The Generator mode provides an automatic cyclic start of program execution. For-, starting the IR in different modes is performed by block 11. The starting frequency depends on the signals of the Frequency Code from the console 12. In addition, block 11 provides synchronization of two F when checking the channel-channel-type adapter. If the Master mode is set, then this G will synchronize the operation of another IR, sending the initial setup signal via bus 14 to it. If the Lead mode is not set, then the G is synchronized by another G, receiving the signal of the initial installation via bus 13 and transmitting it to block 3.

The control unit 3 is implemented in the form of a firmware automaton whose graph-algorithm is presented in FIG. Multiplexer 19 is designed to implement conditional transitions. A permanent memory (ROM) 20 serves 35 to store a set of microinstructions. You- The input register 21 is designed to eliminate the variation in sampling time of the various address bits of the ROM 2-0.

The information inputs of the multiplexer 19 are connected to the input signal buses of the control unit, i.e. signals, which are transitions from one state to another.

45 The output of the multiplexer 19 is connected to the lower address input of the ROM 20, the remaining address inputs of which are supplied with signals from the output register 21 (FIG. 3).

50

In each state of the automat, to which the selected cell of the ROM 20 corresponds, the one of the input signal buses is connected to the address low-order input

by-pass mode (for example, accumulation-, 5 block catch 3. Choice of a plug-in bus

whether on tapes, etc.), such control is carried out in the microcomposition format field using block 10 ,, manda.

which provides an entry in the buffer- micro-command format is presented

Ny register 4 and the following indication is below.

W

t5

20

25

thirty

e

108236

on the remote control 12, the required data byte or status byte. To do this, the number 12 on the order of 12) of the required byte is dialed.

IR in Tact mode provides setting and resetting each interface signal by pressing the button on the remote control 12, in Automatic mode by pressing the button on the remote control 12, the entire program or its part is executed (if the control panel malfunctions). The Generator mode provides an automatic cyclic start of program execution. For-, starting the IR in different modes is performed by block 11. The starting frequency depends on the signals of the Frequency Code from the console 12. In addition, block 11 provides synchronization of two F when checking the channel-channel-type adapter. If the Master mode is set, then this G will synchronize the operation of another IR, sending the initial setup signal via bus 14 to it. If the Lead mode is not set, then the G is synchronized by another G, receiving the signal of the initial installation via bus 13 and transmitting it to block 3.

The control unit 3 is implemented in the form of a firmware automaton whose graph-algorithm is presented in FIG. Multiplexer 19 is designed to implement conditional transitions. A permanent memory (ROM) 20 serves 35 to store a set of microinstructions. You- The input register 21 is designed to eliminate the variation in sampling time of the various address bits of the ROM 2-0.

Q

The information inputs of the multiplexer 19 are connected to the input signal buses of the control unit, i.e. signals, which are transitions from one state to another.

45 The output of the multiplexer 19 is connected to the lower address input of the ROM 20, the remaining address inputs of which are supplied with signals from the output register 21 (FIG. 3).

50

In each state of the automat, to which the selected cell of the ROM 20 corresponds, the one of the input signal buses is connected to the address low-order input

If an input signal is present on the selected bus (i.e., 1), the automaton enters a state in the lower order of which there is a one. If there is no input signal on the selected bus (i.e., O is present), then the machine enters a state in the lowest address bit of which there is a zero. For example, let the address field of the ROM represent the combination of OOP, the address field of the input multiplexer 19 is 0101. If the input signal (i.e., 1) is present at the fifth input of the multiplexer 19, then the transition is performed at address 00111, if there is no input signal This transition is performed at address 00110. All other conditional transitions are implemented in the same way (Figure 4).

To generate the output signals of block 3, horizontal microprogramming is used, i.e. Each bit of the field of microcommand output signals corresponds to a certain output signal of block 3.

Amplifier transmitters 22 and 25 of block 2 (FIG. 5) are designed to amplify the signals transmitted in the control panel, and amplifiers-receivers 23 and 24 - to enhance the signals received from the control panel. Control of the definition of bytes received from the control panel is carried out using circuit 26. Circuit diagram 27 compares the control panel number transmitted via TIR-K with the control number received on bus-A, with the result in block 3, using the scheme 28, a check-byte of the byte transmitted to the control panel is formed with transfer to the control panel.

The 29 state byte decoder defines the type of status byte. Through switch 30 in block 2 enin arrives

20

25

When specifying the data (type of work Programming), the latter are stored in memory 31 from remote control 12 at the addresses specified from remote control 12 and delivered to address inputs through commutators 32 and 33 (fig). When reading data (type of operation, the Control PU from memory 31 is entered into register 8, and the address of the selected data is determined with or data counter 35 data (the high and low bits of which are received at the address inputs of memory 31, respectively) 32 switches and 33), or the lower bits of the counter 35 and the field value of the current control word BPD.This will allow you to use block 5 either as a single storage device or as several independent smaller storage devices. necessary when performing chains and control words involving the transfer of various data sets to the control center.

thirty

When the counter reaches 35, the value contained in the control frequency field of the control word, which is fixed by the comparison circuit 34, the exchange end signal is transmitted to block 3, which the latter enters into the control unit through block 2 the exchange end sequence. Circuit 34 and counter 35 operate regardless of how the operation (sending or receiving data) is specified in the control word.

The selective display unit 10 provides for writing to the register 4 and the subsequent indication on the console 12 of the required data byte or byte: state (Fig. 8). To do this, on the console 12, the number (in order) of the required byte is dialed, which enters block 10 via buses 45 to the first information inputs of the comparison circuit 42. The counter 43 is preset from the remote control 12 by a signal. Resetting on bus 46. The signal byte of data on push 47 or status byte on bus 48 goes through the OR 44 element to the counting input of counter 43 and modifies its value. If the value of the counter 43 and the code on the tires

40

45

50

formation either from register 9 controllers- 45 Number of bytes, as well as with leading words (when the control number is supplied), signal availability Resolution on the bus is either from the data register 8, or from the data generation unit 7 (during data transmission to the control panel) about

49 (formed by block 3 in the presence of the selection BLOCK mode enabled), the comparison circuit 42 executes the sigO

five

0

five

When specifying the data (Programming work type), the latter are sent to memory 31 from the console 12 to the addresses specified from the console 12 and arriving at the address inputs through switches 32 and 33 (fig). When reading, the data (control type PU) from memory 31 is entered into register 8, and the address of the selected data is determined either by the values of data counter 35 (the high and low bits of which are fed to the address inputs of memory 31, respectively) -32 and 33), either by the lower bits of the counter 35 and the field value of the BAP of the current control word. This allows block 5 to be used either as a single storage device or as several smaller independent storage devices. The latter is necessary when executing a chain of control words involving the transfer of various data arrays to the control center.

0

When the counter reaches 35, the value contained in the control word of the control word, which is fixed by the comparison circuit 34, is transmitted to block 3 by the exchange end signal, through which the latter enters into the control unit via block 2 the exchange end sequence. Circuit 34 and counter 35 operate regardless of how the operation (transmitting or receiving data) is specified in the control word.

The selective display unit 10 provides for writing to the register 4 and the subsequent indication on the console 12 of the required data byte or byte: state (Fig. 8). To do this, on the console 12, the number (in order) of the required byte is dialed, which enters block 10 via buses 45 to the first information inputs of the comparison circuit 42. The counter 43 is preset from the remote control 12 by a signal. Resetting on bus 46. The signal byte of data on push 47 or status byte on bus 48 goes through the OR 44 element to the counting input of counter 43 and modifies its value. If the value of the counter 43 and the code on the tires

0

five

0

45 Number of bytes, as well as when there is a signal. Bus resolution

49 (formed by block 3 in the presence of the selection BLOCK mode enabled), the comparison circuit 42 shows the sign 910310310

An entry in the register A of the data byte 40 is calculated by the number of the over- or the state coming from the control panel. data bytes and circuit 41 compares

In the absence of signals, the Complex with the quantity specified in the corresponding bus 63 and the generator on the bus 61 is in the control word field. Sig signal Resetting the console on the bus 62 from .5 the comparison is sent to block 3. Console 12 through the element 55 comes in. Consider the operation of block 3 controls the element OR 59, and from its output (T) it is the algorithm through the elements And 52 and OR 50 - in (figure 4),

block 3. According to this signal, block 3, to the initial state of the SU, corresponds to the launch of the IR. If available, it signals the state O of its graph. Only the voltage on the bus 61, the generator 56, and the separation in the initial state O is absent. The frequency tele 57 forms the peer-signal group RAB-K at the output of the SU. When given periodic signals from different parts of the Control mode of the control panel on the console. One of these signals after 12 (no signal of the Programmer Switch 58 and the entry And 54 is arriving), the transducer from the state O goes to the input of the OR element 59, and from it goes to the state 1 directly through the output And 52 and OR 50- after pressing the button on the remote control 12 in block 3 and organizes periodic modes Automatic and Tact (presence of IR start, Start frequency depends on the Start signal and no signal on the signals Frequency code on the bus 20 of the Generator) (or through state 60 coming from the control panel 12 to the control - 2 in the Generator mode), the input inputs are switch pa 58. Block 11 g state 1 W PE analyzes also provides sinhronvdatsiyu hours: unit 6 (vsholnenie works two IR checking PU type multiple commands) or with register channel 9 adapter channel. In this case: (execution of a single command) the mode Complex is set by the remote control 12. ZUK signal from the remote J2. If If the mode is also set to Lead to work with block 6, UU produces (signal on bus 64), then this IR call signal to block 6 OBR.ZUK synchronizes the operation of another IR, you- (state 3). After giving him a bus 14 (through the elements of -30 controlling her word from block 6 AND 53) a signal of the initial installation. .will be recorded from register 9 (if-; If the Master mode is not set, then the “e signal of the RESPONSE of the power supply unit from block 6), this IR is synchronized by others and starts to establish communication with the IR, receiving the initial-jjy signal via bus 13 four),

of the installation and transmitting it to the 35 g block of state 4 of the UA, it is developed 3 through the elements AND 51 and OR 50. DDP that enters

In the operator's panel 12 (FIG. 10) to the input of block 2. According to this signal, the code of register 65 serves to store the signal number of the PU from register 9 through the interface switches, elements 66 of the indicator -Qor 30, and amplifiers-transmitters 25 - to indicate the status of the register unit 2 is fed to the bus 1. In countries 4, 8, 9 and 65, toggle registries 5 UU, signals 67, 68, 69 and 70 are generated - to set the co-WWR-K and ADR-K, which through the amplitudes of the bytes for the block 10, byte-transmitters 22 of block 2 provide data for block 8 and control green. on buses 1. From the control panel to the control unit through amplifiers for block 9, the frequency code for block 23 of block 2 receives signals RAB-A, ka 11, the address for blocks 5 and 6, re-ADR-A, and also the result of comparison the mode switches 71 for setting the addresses from the output of the circuit 27 of the comparative modes of blocks 3, 5, 6 and 11. (ADDRP signal), In the absence of a signal, the Register 38, the ROM 39 and the counter 40 of the ALRSP UU switch to 6, ka 7 (Fig. 7) form arrays of numbers, 7, 8 and returns to the original transmitted to the PU, the switch 37 on the state O, removing the VBR-K signals, the indicators coming from block 9, AD RK, RAB-K „

selects one of three sources of these. If the ADRSP signal is present from the VU from numbers - register 38 or ROM 39, or state 5 enters counter 40. Pointers are stored in 9, removing from the input of switch 30 the corresponding control field signal OUTP. signaling the OUT. the words. Regardless of which of the CPC., According to which the output of the switch of the three sources of numbers is selected, the account-30 passes the operation code from the register

fO

111310823

9. In state 9, the ADR-K signal is removed, while operating in multiplexed mode, the FBG-K signal (no monopole signal). In state 10, the UU generates a UPR-K signal, which via amplifiers-transmitters 22 is fed to buses 1. The control unit receives the operation code responding with a status byte, followed by an UPR-A signal. The status byte arrives from the outputs of the amplifier-receivers 24 to the input buffer register 4, node 26, and decoder 29 of block 2. The results of decoding (signals of the zero byte of BS-0 state, final byte of TC, byte with a pointer Attention - HV signal) and definition control come to the SU. On the signal UPR-A, the control unit switches to the state P, removing the signal for issuing the operation code and the signal UPR-K. From state 11, through state 12, the CU enters state 13. In state 13, the INF-K signal is generated. Depending on the result of decryption

12

20

honestly transmitted bytes with the number of bytes specified in register 9 (KCCHS). If the CCCHP signal is absent, then the CU from the state 23 transfers 5 to the state 21, the IR receives from the control panel (or transmits to the control panel) the following information bytes. If there is a KChSOVP signal, then the LU goes to state 24, transmitting through the amplifiers-transducers 22 to the PU, the termination signal is about UPR-K. After the INF-A signal is removed, the SU switches to state 25 and removes the UPR-K signal. And state 25 of the control unit goes into state 17, waiting for the response of the control unit.

If the CU is in state 2a, the RAB-A, UPR-A signals come from the control panel, or the RAB-A signal is removed, the CU also goes to state 17 and then into states 12 and 18, respectively.

In state 18, the CC analyzes the signals of the CC (command chain pointer) from register 9, TC, HV from

15

the status byte and the code of the operator, the encoder 29. In the presence of signals

In the register 9, the control unit switches to state 14 or 16, and then to state 15. From state 15, after the control signal is removed from the control panel, the control signal goes to state 17, and the signal INF-K is removed. In state 17, the CU analyzes the PU. When the control unit's byte transmits byte, the control unit enters state 17, when the control panel outputs an INF-A signal, it transits to state 21,

switching off the control panel (deactivation of the RAB-A signal) to state 18, I

In state 21, the LU generates a byte counting signal + 1 SCH received at the counting input of the counter 40 of block 7, a signal giving information to the control panel OUTPH.INF when executing the Write operation (presence of the operation code Record at the output of the register 9) 30 of block 2, the INF-K signal. When executing the operation, reading information from the control panel from busses 1 through amplifiers-receivers 24 of block 2 is fed to the input of node 26 and the input of block 4. After the control panel has removed the signal INF-A, the control unit goes to state where the signals are taken INF-K, VYD.INF. CU analyzes in state 22 the presence of signals

INF-A, UPR-A, RAB-A from PU. When the initial state of O was found, the signals of the INF-A signal of the VU were cleared to the RAB-K cash.

state 23, where ana is produced. If the CU is in the initial state of the signal from the output of the circuit 41 comparing with and comes from the control unit through block 7 (the signal of the match of 1 of the interface signal TRB-Aj, sig12

O

0

honest transferred bytes with the number of bytes specified in register 9 (KCCHS). If the CCNP signal is absent, then the CU from state 23 switches to state 21, the IR receives from the control panel (or transmits to the control panel) the next byte of information. If there is a KChSOVP signal, then the UU switches to the state 24, transmitting through the amplifiers-transmitters 22 to the PU, the signal of the end of the UPR-K exchange. After the INF-A signal is removed, the SU switches to state 25 and removes the UPR-K signal. From state 25, the control unit goes to state 17, waiting for the response of the control panel.

If the CU is in state 22 and the RAB-A, UPR-A signals come from the control panel, or the RAB-A signal is removed, then the CU also goes to state 17, and then to states 12 and 18, respectively.

In state 18, the CC analyzes the signals of the CC (command chain pointer) from register 9, TC, VN from de5

 encoder 29. When signals are present

0

five

0

0

CC and TC (which indicates normal completion of the operation) of the control unit goes to state 19, where the signal + 1СЧ ЗУК is formed, which enters through block 6 to register 9, and the control word from the scan program is recorded. In state 19, a signal is triggered to start a timer on which counter 17 of block 15 is zeroed. When the value of counter 17 coincides with the time delay interval (the presence of a VZ-T signal at the output of the comparison circuit 18) specified in the VZ of the control word, Woo goes into. state 20, If the OZ control word field contains zeros, then the signal at the output of the comparison circuit 18 is formed immediately after the start of timer 15. From state 20, the control unit goes to state 1. I

In the presence of a high-frequency signal and the absence of a signal, the CC of the control unit switches to the state. 20, and then in state I, of entering into the control panel of the same operation, the code of which is stored in register 9. In the absence of signals from the CC and VN VU, through state 8 it goes into

cash BOR-A is absent, thenUU goes to. state 28, where the FBR-K signal is generated. Upon receipt of the signals RAB-A, ADR-A of the CU from the PU, it enters state 27, where the signal is taken

Of

FIG. 2

UBR-K and the UBR-K signal is generated, the UU in state 27 analyzes the ADR-A signal, after the ADR-A signal is removed, the TC goes to state 17, removes the UPR-K signal, and waits for the response of the PU.

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Editor M. Dylyn

Tehred L. Oliynyk

Order 1892/45 Circulation 673. Subscription VNIISH State Committee of the USSR

for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5

Production and printing company, Uzhgorod, st. Project, 4

Proofreader M. Pojo

Claims (1)

CHANNEL SIMULATOR No. 1174927, characterized in that, in order to reduce the verification time of the peripheral device, a time counter unit is included in it, including a time stamp generator, a counter and a comparison circuit, the output of the time stamp generator being connected to the counter input of the counter, the first input of the comparison circuit connected to the output of the control word register j the counter output is connected to the second input of the comparison circuit, the counter reset input and the output of the comparison circuit are connected respectively to the fourth input and second output of the control unit. Figure 1 Titi