SU1305684A1 - Device for generating modulo remainders - Google Patents

Description

group, the transfer output of the pth single-bit adder of the group is connected to

one

The invention relates to computing and is intended to form residuals by modulus of Mersenne numbers, which are of the form Mp 2 -1, where p is a prime number and is used in digital signal processing.

The aim of the invention is to expand the field of application by forming residues modulo the Mersenne numbers.

FIG. 1 shows a diagram of an apparatus for forming residues modulo; in fig. Figure 2 shows the convolution block diagram

A device for forming residues modulo (Fig. 1) contains single-bit adders 1.1-l.p combined into groups 2.1-2 (1-1), a convolution unit 3, an inlet 4 of a convolution unit 3, and an output 5 of the device. The convolution unit 3 (Fig. 2) contains a group of elements AND 6.1-bp, an element EXCLUSIVE OR 7, an element AND 8, a group of one-bit adders 9.1-9.r.

The principle of operation is based on the following considerations.

The initial number A can be represented as a polynomial.

 A, +

A, .2

+ Aj .2

2P

+

(one)

The remainder of dividing the multi-digit number A by the modulus of the Mersenne number NO is equal to the remainder of dividing many p members

(1) on this module

And Mr AO + A, + AJ Mr, (2)

where AO: A ,, Aj ... are consecutive groups of binary numbers in p bits of binary digits, starting with the least significant bits.

In accordance with (1) and (2), the weight of the p-th bit of the sum (2) is equal to the weight of the cached bit, due to which the transfer output of the first one-bit adder of the group.

The transfer ports of the highest p-bit adders can be connected to the lower-end carry ports. This makes it possible to synthesize a rectangular matrix of adders with a horizontal chain of propagation of the transfer signal.

At the output of the matrix of adders, there should be a convolution block whose purpose is to convert the input (p + 1) bit code into a p-bit residue.

A device for forming residues modulo (Fig. 1 and 2) works as follows.

Consider the operation of the device by the example of the formation of the remainder of a 32-bit modulo Mj 7.

The original 32-bit number (Fig. 1) is divided into three-digit numbers A ... .... In this case, the device contains groups 2.1–2.10, in each of which there are three adders 1.1–1.3, and in group 2.10 there are two adders, since the number is two-digit.

In the first group 2.1, the sum A + A is obtained. In the subsequent groups, the result obtained is added to the next number A, while the transfer unit is summed up with the least significant bit.

In block 3, the And 8 element does not prevent the passage of signals from input 4 through And 6 elements to the inputs of adders 9, since if there is at least one zero signal at the input of the And 8 element, there will be a single signal at its output. Only the code with all the single signals will go to the inputs of the adders 9 in the form of zero signals. The validity of this transformation follows from the fact that the residue 111

0

five

0

five

0

five

modulo M,

 Yu

111 is equal to 000.

/ It

flft-f - OLP

Ai

AO

Oyp.f ... OZP QZP-t Op 0

Ai

AO

Ko / 4,

Ag

/ At- /

Ki

C.R.

V. (). $ ,, /

Editor G. Gerber

Compiled by A, Klyuev Tehred A. Kravchuk

Order U53 / 47 Circulation 673 Subscription

VNIIPI USSR State Committee

for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., D / 5

Production and printing company, Uzhgorod, st. Project, 4

Proofreader L. Pnlipenko

Claims (1)

DEVICE FOR FORMING RESIDUES BY MODULE, containing (1-1) a group of single-bit adders (Έ = η Ί -, where η is the bit capacity of the number, pР J is a prime number), and the inputs of the first and second terms of single-bit adders of the first group are connected respectively to the first and the second group of p bits of the information input of the device, the outputs of the sum of single-bit adders of the i-th group are connected to the inputs of the first term of the corresponding single-bit adders (i + 1) of the ί group = 1- (1-2), the inputs of the second term of the single-digit adders (1 +1) th g spp are connected, respectively, with bits of the (1 + 2) th group of the information input of the device, characterized in that, in order to expand the scope by forming residues modulo Mersenne numbers, it contains a convolution block containing a group of single-digit adders, a group of AND elements, an EXCLUSIVE OR element, and AND element, and the transfer output of the k-th single-bit adder of the i-th group is connected to the transfer input of the (k + 1) -th single-bit adder of the i-th group, the transfer output of the r-th single-bit adder of the i-th groups connected to the house entrance transfer of the first one-bit adder of the (1 + 1) -th group, transfer output of that one single-bit adder of the last group (a = 1-s-1; s = np (I-2) is connected to the transfer input of the (t + 1) -th 'one-bit adder of the last group, the outputs of the sum of the one-bit adders of the last group, the outputs of the one-bit adders from (s + l) -ro in (p-p) - of the penultimate group and the transfer output s-ro of the one-bit adder of the last group are connected respectively to the first inputs of the AND elements of the convolution block group, the outputs of the sum of the one-bit adders of the convolution block are the output of the device, and in the convolution block the transfer output of the k-th one-bit adder is connected to the transfer input ( k + 1) th odor of a single adder (-k = 1-p-1), the inputs of the (p + 1) -th and (s + 1) -ro elements AND groups are connected respectively to the first and second inputs of an EXCLUSIVE OR element, the output of which and the first inputs of AND elements , in addition to the (p + 1) th and (s + 1) -ro groups, respectively, are connected to the inputs of the element AND, the inverse output of which is connected to the second inputs of the elements of the And group, the outputs of which, except the (p + 1) th, are connected to the inputs of the first terms of the corresponding single-bit adders of the group, the output of the (p + 1) -th element AND of the group SU, „. 1305684 dinen with the input of the second term (s + 1) -ro of the one-bit group adder, the transfer output of the r-th one-bit group adder is connected to the transfer input of the first one-bit group adder.