SU1298832A1 - Frequency multiplier - Google Patents

Abstract

Invention m. used in FM transmission systems. The purpose of the invention is to improve the accuracy of frequency multiplication. The device contains a pulse shaper 1, an integrating unit 3, a comparators unit 12, a multi-input adder 13, a band-pass filter 14. The delay element 2 is newly introduced, the memory units 4-6, the reference voltage source 7, the subtraction unit 8, multiplier 9, divider of 10 voltages, adder 11. 2 Il. / 1 ju co oo with 00 GS

Description

The invention relates to radio engineering and can be used in the transmission systems of frequency-modulated signals.

The purpose of the invention is to increase the frequency multiplication accuracy.

FIG. functional diagram of the frequency multiplier is presented; Fig. 2 shows timing charts for the operation of the multiplier.

The frequency multiplier contains a pulse former 1, a delay element 2, an integration unit 3, a first 4, a second 5 and a third 6 memory elements, a reference voltage source 7, a subtraction unit 8, a multiplier 9, a voltage divider 10, an adder 11, a block 12 comparators, multi-input adder 13 and band-pass filter 14

The frequency multiplier works as follows.

A harmonic signal or a periodic sequence of pulses is input to the pulse generator 1 (Fig. 1), and a sequence of short pulses is formed at its output (Fig. 2a), the instants of which coincide with the leading edges of the input pulse sequence or from the transition moment through zero (with a positive derivative) of the input harmonic frame, and delay element 2 delays these pulses. The delay time is chosen so that the transients in the elements of the circuit are transmitted (Fig. 2a, b).

The input voltage of the integration unit 3 and (on the N-M period fell

IN g. 9J

.

impulses, fig.2g) comes from the output of the second memory element 5. Maximum output voltage. block 3 integration (figv) at the end of the K-th period of the input signal

m

UMOKC .N

Where

 N

Int

-time interval between two pulses;

-Integration of the integration unit 3.

At time t (Fig. 2a), the first memory element 4 is recorded and the third memory element 6, Uj. To the first input of block 8, the subtraction enters and, from the output of the source 7 of the reference voltage. Differential voltage

-UN and. - ai „g,“ flT

From the output of block 8, the subtraction is fed to the first input of the multiplier 9, to the second input of which is supplied a voltage from the output of the 10 voltage divider, equal to

and

e. "

N

  HHT.N (Ing.m T

multiplier

Thus, the output voltage 9

and, U .. U ;, and .. - and.,

 N

Cm. M 5.N about G, INT.K

This voltage is applied to the first input of the adder 11, the second input of which receives the voltage from the output of the third memory element 6. The input to the second memory element 5 is voltage

 .

-35

and,

 and,.

+ and

20

25

INT-N + i

At time t

) u.N

block

 and.

IN1

3 integ- na0

thirty

40

45

The drawing is installed in the string C, " | .. i is stored in the second memory element 5 and is fed to the information input of the integration unit 3. Assuming that Cp, f N4-i we get that at the end of the (N + l) -ro period and „o,„., O Thus, under the condition 4Tot |,, the output of the integration unit 3 will be a sawtooth voltage, which has - UQ This voltage is compared in a block of 12 comparators

with M thresholds and 0 ° C

 2y

M

Comparator block 12 appears pulses, which at the output of the multi-input adder 13 form a periodic sequence of pulses with a tracking frequency f-M, where f is the frequency of the input signal. Band-pass filter 14 is required to obtain a sine-wave signal at the output of a frequency multiplier.

 (m-12i „M

and exit 5 (

Formula

of

gaining

A frequency multiplier comprising a serially connected integration unit, a comparators unit and a multi-input adder, a pulse shaper and a band-pass filter, characterized in that, in order to improve the frequency multiplication accuracy, the first connected memory element, subtractor unit, multiplier, adder are introduced.

the second memory element and the third memory element, the voltage divider, the source of the reference voltage, the delay element, whose input is combined with the recording input of the first and third elements of the memory and connected to the output of the pulse former, and the output of the delay element is connected to the recording input of the second memory element and the reset input of the integration unit, the signal input of which is combined with the first input of the voltage divider and connected to the output of the second element

Goo.

N1

N

memory, the output of the integration unit is connected to the information input of the first memory element, the electrode of which is connected to the second input of the voltage divider, the output of the voltage divider is connected to the second input of the multiplier, the output of the third memory element is connected to the second input of the adder, the output of the reference voltage source is connected to the second input of the subtraction unit, the output of the multi-adder is connected to the input of the band-pass filter.

Editor V. Petrash

Compiled by Y. Maximov

Tehred M. Morgental Proofreader A. Zkmokosov

Order 894/55 Circulation 902 Subscription

VNIIPI USSR State Committee

for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5

Production and printing company, Uzhgorod, Projecto st., 4

2

Claims (1)

The claims) A frequency multiplier comprising a series-connected integration unit, a comparator unit and a multi-input adder, a pulse shaper and a band-pass filter, characterized in that, in order to improve the frequency multiplication accuracy, the first memory element, the subtraction unit, the multiplier, the adder are introduced in series, 1298832 4 second memory element and third memory element, voltage divider, reference voltage source, delay element, the input of which is combined with the recording input of the first and third 5th elements of memory and connected to the output of the pulse shaper, and the output of the delay element is connected to the recording input the second memory element and the reset input of the integration unit, 10 whose signal input is combined with the first input of the voltage divider and connected to the output of the second memory element, the output of the integration unit is connected to the information input the first memory element, the input of which is connected to the second input of the voltage divider, the output of the voltage divider is connected to the second input of the multiplier, the output of the third memory element is connected to the second input of the adder, the output of the reference voltage source is connected to the second input of the subtraction unit, the output of the multi-input adder is connected to the input of the strip filter. ΝΊ period N-U. period tN-1 Ν + 7 -u period χ In 'En | t tN * 1 I I t'ri-g I  I tN-1! I 1 1 Jj i dmax ^ . I I ------ Ί ^- I ---------- h I UuHm // + 1 j FIG. 2