SU1296958A1 - Adaptive device for analyzing digital signals - Google Patents

Abstract

The invention relates to the field of radio engineering and can be used in digital information processing systems of coherent-pulse radar stations with a circular or sectorial survey of space. The purpose / invention is to increase the speed of the device. The adaptive device comprises an analog-to-digital converter 1, an interference suppression filter 2, and a block 4 of a discrete Fourier converter. The unit has been introduced; block 3 for reducing the size of,; including an encoder and p parallel channels, each of which is made of a series-connected OR element and a key. The introduction of the specified block reduces the size of the source data being processed. In this case, it becomes possible to make an adaptive change in the size of the processed numbers. 1 hp f-Jl, 2 ill. S (L phi & 1 o to with O5 CO. SP 00

Description

; The invention relates to radio engineering and can be used in digital information processing systems of coherent pulse radar stations of a circular or sectorial review of space for analyzing digital signals.

The purpose of the invention is to increase the speed by reducing the time of calculating the discrete spectrum by reducing the width of the processing of raw data with the help of the block of reducing the bit size, which allows for an adaptive change in the size of the processed numbers, which leads to an increase in speed and decrease analysis time.

Figure 1 shows the structural diagram of the proposed device; Fig. 2 is a block diagram of the minimization unit.

The device contains serially connected analog-to-digital converter 1, noise suppression filter 2, reduction block 3, discrete Fourier transform block A, the control input and the output of which are connected respectively to the control output of the decrease block and the combined control inputs of the analog a digital converter, a noise suppression filter, and a bit reduction unit. Block 3 reduces: the bit size saves the encoder 5 and n parallel channels, each of which is made up of the series-connected element OR 6 and the key 7, while the output and input of the bit reduction block are respectively the 10th and second the inputs of the element OR 6, combined with the inputs of the corresponding keys, and the output of the element OR of each channel is connected to the first input of the element OR of the adjacent channel and the corresponding input of the encoder, the control input and outputs of which are respectively control and the input and output of the minimization unit.

The device works as follows.

In a coherent-pulse radar station with a circular or sector view of space, the problem of detecting a signal reflected from a moving object when it is turned off is solved.

0

five

0

five

five

the presence of correlated interference, the power of which, as a rule; n) the emitted power of the useful signal is 60-80 dB. This task is solved by a moving target selection system (MTS). The formation of a stream of digital signals in the system of the SDC is as follows. The analog video signal is input to the analog-to-digital converter from the output of the radar phase detection channel (radar), (not shown) .. Since the dynamic range of the input signal is determined by the power of the correlated interference, the width of the analog-to-digital converter (ADC) I is selected in accordance with the following ratio g d / 6, (1)

where r is the number of binary bits;

c1 is the dynamic range of the input signal, dB.

Based on formula (I), the ADC I width is usually chosen to be 10-12.

Since the Doppler shift of the frequency of the signal reflected from the object far exceeds the maximum Doppler frequency of the interference signal, fb can be suppressed using special interference cancellation filters. In this case, the filter output dynamic range will be reduced.

A decrease in the dm level leads to the fact that some of the high-order digits of a digital code will be all the time zero and only r low-order bits will carry information. 0 Thus, without degrading the accuracy of the data being processed, it is possible to reduce the size of the processed digital codes to r. For this purpose, a reduction unit 3 has been introduced into the proposed device.

The basis of the interference suppression filter circuit is a structural scheme of the known two-pulse interference suppressor.

As the calculations show, with typical values of the correlation parameters, the inter-period interference compensation reduces the number of bits by 3-5.

The analog signal is converted to A / D converter 1 into a parallel code using sampling pulses.

0

five

0

coming from the control output of block 4. As ADC 1, you can use the well-known parallel conversion circuit, which can be implemented using 521CA1-521CA4 compressors and a conditioning element with a priority of K500IV165.

The parallel code enters the interference suppression filter 2, which is a mode-periodic compensation system.

From the output of the interference suppression filter 2, the digital pass code enters block 3 for reducing the bit size d-. bones. Block 3 reduces the input data width and also absorbs the control signal, which is fed to block 4 of the discrete Fourier transform (DFT). The digital code arrives at the second inputs of the SHSh 6 elements as which you can use integrated circuits (IC) K155LL1. In this case, through time t (where t is the time of signal propagation in the OR element), the output of the OR element corresponding to the higher and most bits will establish a logical voltage, which is determined by the state of the most significant bit. This voltage will be applied to the first input of the NL element corresponding to the neighboring highest level. The voltage at the output of this element OR will be set according to the (r-l) -ro state of the discharge. Thus, through time r T at the outputs of the elements OR 6 a parallel unit code of the form will be established:

Open Company ... СЮ111 ... П,

in which the number of zeros is equal to the number of -Significant non-significant bits. This single code enters an encoder 5 which converts it into a parallel binary code, which is the control signal for DFT block 4. encoder 5 is synchronized with sampling pulses. A single parallel code from the outputs of the elements OR 6 is fed to the control inputs of the corresponding keys 7, to the inputs of which the parallel code is applied. As a result, only r of keys 7, corresponding to the younger bits, will turn out to be in a closed state, and, consequently, the size of the input reduction code to r. As keys 7, you can use IC series K514KT1.

From the output of block 3, the digital code enters the block 4 of the discrete Fourier transform, which calculates the discrete spectrum of the signal in accordance with a known algorithm.

The basis of block 4 of the DFT is the known circuit of the digital spectrum analyzer.

Thus, the introduction of a reduction block allows you to reduce the number of presentation bits of the processed data and generate a control signal for the discrete spectrum calculating unit, which reduces the processing time

These advantages are explained by the fact that when calculating the discrete spectrum of the processed signals, fewer bits are used to represent which, the total data analysis time is reduced.

A comparative assessment was made of the performance of the prepaired device and the base object.

Depending on the typical values of the inter-period correlation coefficient and the dynamic range, the input signals of a gain in productivity are equal to 1% from 20 to 45%.

Claims (2)

1. An adaptive digital signal analysis device comprising a series-connected analog-to-digital converter and an interference suppression filter, as well as a discrete Fourier transform unit, the output of which is connected to the control inputs of the analog-digital converter and the interference suppression filter, and the information output is output of the device, characterized in that, in order to increase speed, a diminution block is inserted in it, connected between the output of the interference suppression filter and the information onnym input of the discrete Fourier transform ,, control output of which is connected to the control input of the Yu-1TSIM reduce discharge of clarity, the second output of this the block is connected to the second control input of the discrete Fourier transform block, 2. The device according to claim 1, wherein the reduction block contains an encoder, the control input of which is the control input of the decrease block, and n parallel channels, each of which contains the OR element and the key whose control input is connected to, "/ 1 12969586 the input of the S1I element, in which the input of the diminution block is the second inputs of the OR elements, each of which is connected to the second input of the corresponding key, and its output is the outputs of the keys, and the output of the OR element of each channel, except the last one, is connected to the first input of the OR element of the adjacent JO channel and with the corresponding input of the encoder, the outputs of which are the control output of the minimization unit. Editor A.Revin Compiled by A.Orlov Tehred A. Kravchuk Order 773/47 Circulation 731 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, Projecto st., 4 Proofreader A.Zimokosov