SU1290555A1 - Digital information transmission system - Google Patents

Abstract

The invention relates to radio engineering and provides increased reliability by reducing the likelihood of an undetected error. The digital information transmission system comprises on the transmitting side a control and synchronization unit (BEAD) 1, information encoder 2, switch 3, check encoder 4, block 5. transmission and information source 6, and on the receiving side - WCD 7, switch 8, memory blocks 9, 12, information decoder 10, check decoder 11, check code encoder 13, comparison unit 14, output matching unit 15, decision unit 16 and block 17 of the reception. A code combination (QC) of the information is recorded in the information coder 2. At its output, a QC is formed according to the biorthogonal code principle, which is then encoded by the check encoder 4 according to the principle of the formation of the termination code. The codeogram formed at the output of switch 3 is a systematic two-step code, in which the symbols of the check code follow each information symbol. Upon receipt, the switch 8 divides the received systematic code into information and test QC. In decoders 10, 1 G, they are decoded using the max, likelihood method, which provides decorrelation of errors. Check encoder 13 re-encodes QC. When they coincide, the QC signal of the coincidence unit 14 is recorded in the decision unit 16. 1 pc. (L 1C with about JV ate

Description

The invention relates to radio engineering and can be used in information transmission systems.

The purpose of the invention is to increase confidence by reducing the likelihood of an undetected error.

The drawing shows a structural electrical circuit of the proposed system.

controlled by the control and synchronization unit 7, it separates the systematic code into an information and verification code combination, which are then decoded by the decoders 10 and 11 using the maximum likelihood method, and the inputs of the decoders 10 and 11 are transmitted to the inputs of the decoders 10 and 11. formation and verification codes

The digital information transmission system is from memory blocks 9 and 12, which provide

On the transmitting side, the control and synchronization unit 1, the information encoder 2, the switch 3, the verification encoder 4, the transmission unit 5, the information source 6, and the receiving side, the control and synchronization unit 7, the switch 8, the first memory block 9, information decoder 10,

check decoder 11, the second block. 12 memory, verification code encoder 13, comparison block 14, output matching block 15, decision block 16, receive block 17.

one

The system works as follows: The code combination, coming from the information source 6 to the inputs of the control and synchronization unit 1, starts it, and then is recorded in the information encoder 2. The control and synchronization unit 1 provides control of the operation of the information encoder 2, as well as switch 3 and check encoder 4 in such a way that a code combination is formed at the output of information encoder 2 according to the biorthogonal code principle, which is then encoded by check encoder 4 according to the vani to welding

yes, and from its outputs (there may be n) through the switch 3, the generated codegram is fed to the input of the transmission unit 5. A codogram is a systematic two-step code, in which after each information symbol is followed by a verification code, for example

symbols of information code

11000111.1

-character verification code.

The code combination thus obtained is transmitted through the transmission unit 5 to the communication line, where it is exposed to interference.

The receiving unit 17 has selected a distorted interference combination, and the switch 8,

controlled by the control and synchronization unit 7, it separates the systematic code into an information and verification code combination, which are then decoded by the decoders 10 and 11 using the maximum likelihood method, and the inputs of the decoders 10 and 11 are transmitted to the inputs of the decoders 10 and 11. formation and verification codes

0

50

It is the decorrelation of errors. From the output of the decoder 10, a correctly received code combination (or with undetected errors) is fed to the encoder 13 of the verification code and written into the output matching unit 15. The re-encoded combination by the verification encoder 13, similar to the transmitting side, is fed to the third input of the comparison unit 14, first the input of which is received correctly received (or with undetected errors) the combination of the verification code from the output of the verification decoder 11. If the combinations coincide, the output of the comparison unit 14 forms an enabling parameter the potential that enters the output matching unit 15 and resolves the recording recorded in the last CQI to the decision unit 16. At the output of the comparison unit 14, a resolution potential can be obtained if the same code combinations are received on the comparison circuit.

Claims (1)

Invention Formula A digital information transmission system comprising, on the transmission side, a source of information, the output of which is connected to the first input of an information encoder, the output of which is connected to the first input of a verification encoder, and a transmission unit and on the receiving side, the receiving unit, the information decoder, the verification decoder and the output matching unit, the output of which is connected to the input of the decision unit, so that, in order to increase the reliability by decreasing the likelihood of an undetected error, the P switch is inserted on the transmitting side control and synchronization unit, the input of which is connected to the first input of the information coder, the second input of which is connected to the first output of the control unit and syn synchronization, the second output of which is connected to the first input of the switch, the second input of which is connected to the first input of the check encoder, the second input of which is connected to the third output of the control and synchronization unit, while the outputs of the checking encoder are connected to the third input of the switch, the output of which is connected to the input of the transmission unit, and at the receiving side, a comparison unit, a verification code coder, two memory blocks, a switch and a control and synchronization unit, the first output of which is connected to the input of the reception unit, are entered, he first output connected to the first input of the switch, the second input of which is connected to the second output of the control and synchronization block, the third vpsod which is connected to the first input of the decoder information and to an input of the first block memory, which output is connected to a second input information deco dera, the third input is connected to the first output of the switch, the second outputs of which are connected to the first inputs of the verification decoder, the second input of which is connected to the output of the second memory block, the input of which is connected to the fourth output of the control and synchronization unit and to the third input of the verification decoder whose input is connected to the first. the second input of the comparator unit, the second input of which is connected to the fifth output of the control and synchronization unit, the sixth output of which is connected to the first input of the output matching unit, the second input of which is connected to the output in comparing unit, a third input of which is connected to an output check code encoder having a first input connected to the seventh output control and synchronization block input coupled to a second output of the receiving unit, wherein the output is connected to an information decoder Auto -; With the input of the encoder check code.