SU1285563A1 - Pulse generator - Google Patents

Abstract

The invention can be used in various digital and analog-digital devices of automation and computing, for example, in a counting type time relay. The purpose of the invention is to improve the accuracy of setting the period of a trace of pulses — achieved by reducing the error of setting the period of following of pulses on a uniform scale of the unit of resistance, the time of the driving resistive circuit. Another goal is to increase the generator reliability by eliminating the possibility of opening a parasitic thyristor structure in the threshold logic circuit. The generator contains a threshold logic circuit 1, a time specifying a resistive circuit 2, a capacitor 3, a resistive regulating body 4, a resistor 5, a bus-8 isg. power point, bus - common 9 and output 10. Circuit 1 contains logical inverters 13, 14 and 15. Chain 2 contains variable I6 and trim 17 resistors, knob 18 and dial 19 with evenly spaced marks 21 and 22, pointer 20 To achieve this goal, resistors 6 and 7 and new functional connections are introduced into the generator. 1 hp f-ly, 2 ill. (О С N9 00 ate О1 о со

Description

The invention relates to a pulse technique and can be used in various analog and digital automation devices and computing, for example, in a counting type time relay.

The purpose of the invention is to increase the accuracy of the pulse period setting by reducing the error setting of the pulse pulse period on a uniform scale of the resistance sensor, setting its resistive circuit and increasing the reliability of the pulse generator by eliminating the possibility of opening a parasitic thyristor structure in the threshold logic circuit .

FIG. 1 is an electrical schematic diagram of a pulse generator; Fig. 2 shows timing diagrams of voltages and currents in some electrical points and circuits of a pulse generator.

The pulse generator contains a CMD threshold logic circuit 1, a time specifying the resistive circuit 2, a capacitor 3, a resistive control switch 4, a first 5, a second 6 and a third 7 resistors, a power supply bus 8, a common 9 and a bus output 10. The first input of the circuit 2 is connected to the inverse output of the circuit 1, the second input is connected to the first plate of the capacitor 3 and the input of the circuit 1, the first terminal of the resistor 5 is connected to the bus 9., the second output is connected to the second inputs of the regulator 4 and the capacitor 3. The first input of the regulating The organ 4 is connected to the direct output of the circuit I through a resistor 6, the second terminal of the resistor 5 is connected to the bus 8 via a resistor 7. The buses 8 and 9 of the generator, pulses are connected to the power bus 11 and to the common bus 1. Scheme 1 accordingly. Iina 10 is connected to one of the outputs of circuit 1, for example, with its inverse output.

Scheme 1 is implemented on known KMDP logic elements so that if there is a positive supply voltage on its bus 11, acting on its bus 12 and

five

0

five

range of load resistances, it has the following characteristics. tikami:

1. When the input voltage is in the range from zero to the first threshold value, the voltage on the forward and inverse outputs are within the limits of the voltage of logical zero and logical unit defined for these outputs, respectively. When the voltage at the input, which is in the range from the second threshold value to the value of the supply voltage, the voltage at the direct and inverse outputs are

within the specified limits of the voltages of the logical unit and logical zero, respectively. The second threshold value is greater than the first threshold value by an amount constituting a small portion, e.g. a few percent, of the input voltage range from zero to the value of the supply voltage, hereinafter referred to as the input voltage range. Both threshold values are in the middle part of the operating range of the input voltage, for example, within the Limits of 30-70% of the value of the supply voltage, and the dependencies of the output voltages on the input voltage in its operating range are monotonic, the output voltage of logical zero is close to zero and the output 5 voltage of the logical unit is close to the value of the supply voltage.

2.When input voltage is in its operating range,

0 input impedance is

. tens or hundreds of mega6m, and the input current in absolute value does not exceed several units or tens of nanoamps. At input voltage

5 outside its operating range, the circuit may have a significantly lower input impedance and a much higher input current, in particular, circuit 1 may

0 to be equipped with the first stash 1t diode, the cathode of which is connected to the input of the circuit 1, the anode with a length of 12, and the second protective diode, the anode of which is connected to the input of the circuit i, ka0

A tire in a certain working cyan-55 bus 11. For example, the scheme

supply voltage, and with external loads on its outputs, having equivalent ohmic resistances in a certain working

1 can be made in the form of series-connected logical inverters 13-15, as which any CMD can be applied

combinational logic elements included in inverters in a known manner, for example, KMDP-logic 2Y-NOT elements, the first inputs of which are used as inputs of inverters, and the second inputs are connected to the power bus, including logic elements from the composition known as KMDP integrated logic circuits, at the inputs which are protective diodes.

The circuit 2 is made in a known way so that, between its first and second inputs, has an ohmic resistance R equal to the sum of two parts. The first part R is directly proportional to the magnitude of the mechanical or electrical setting signal generated by the built-in or external setting device, the second part R is selected when adjusting the pulse generator during its manufacture or during periodic routine adjustment and has during the whole period of operation or during each interregional term, i.e. between routine adjustments, a constant value. As a result, during the operation of the pulse generator, the resistance R can be set smoothly or discretely with the help of a setting unit ranging from a certain minimum value, which is equal to the value set when adjusting the pulse generator, -Contant | Resistance R, to some maximum value K. , is equal to the Max x sum of the maximum value of the resistance R, corresponding to the upper limit of the change of the driving signal, and the value of the resistance R set in a specified manner. Moreover, at least some values of the reference signal correspond to a certain nominal value of the period T following the output pulses of the pulse generator (hereinafter referred to simply as the period) from the specified range of its installation, in particular, the nominal lower and upper limits of the installation T, using circuit 2. Adjusting the range of change of R currents - the ratio to be when adjusting the pulse generator is changed relative to its average value equal to the ratio

either way in

0

five

0

five

0

T / T Mr. 6.P. no. n.number of times, which is selected depending on the possible deviations from the nominal or typical values of the parameters of the applied elements of the pulse generator, affecting the period, for example, 1.5 times. The value of K is preferably in the range of 10-10 ohms, and the value is not less than ohms. For example, circuit 2 contains a variable resistor 16 with a circular movement of the slider, which has a nominally linear dependence of the resistance on the angular position of the slider, and a trimming resistor 17 connected in series, as well as a setting device consisting of a knob 18, which is fixed on the axis of the resistor 16, uniform circular scale 19 mounted or applied concentrically with respect to the axis of the resistor 16 either on the handle 18 or on the housing or other structural support of the pulse generator stationary relative to the housing Stora, b and indicator 20 which is fixed or supported on the carrier concentration str5T tive parts at the first or on the handle at a second of said Ba riant§ positioning scale 19.

The scale contains evenly spaced marks, the extreme of which 21 and 22 are digitized by the given values of T ;, „„. П. .v.p Angle range of the scale between it. the extreme marks are chosen such that they do not exceed the angular mixing range of the resistor slider, 16, in which this resistor has the linearity characteristic specified for it in specifications. The handle 18 is fixed on the axis of the resistor 16

so that when the pointer 20 coincides with the mark 21 of the scale, the resistance of the resistor 16 is close to the minimum possible value, however, outside the region of the initial jump of the resistance of this resistor, if this roll is significant. Resistance R is the portion of the resistor 16 used to set the period,

2- the resistance R is the sum of the established resistance of the resistor 17 and the part not used for adjusting the period from the side of smaller values of resistor 16.

The regulator 4 is made in the form of a variable resistor and provides a smooth or relatively small resolution setting of the resistance R. from zero to the maximum value of R,

 I max.

Resistances of resistors 5-7, hereinafter referred to as R, are forks that the ratio R

R

r, and .. ,,

1 hIkj U1 cisplas jt AND R- is mostly close to the ratio of the maximum permissible flowing current of the logical unit to the maximum permissible flowing current of the logical zero of the direct output of the applied circuit 1, and R is not less than the calculated resistance of the parallel connection of resistors 5 and 7, and mostly close to this magnitude. In addition, in the three-port network, formed by organ 4 and resistors 5-7, when connecting its first and second inputs, which are unconnected directly between themselves by inputs of resistors 5 and 7, to 9 and 8 respectively, between which is applied E of the power supply of circuit 1, which is in the working range of its supply voltage, and with zero resistance of the organ, 4 current values that occur through the resistor 6 when the third input of the mentioned three-pole is connected, which is not connected directly but with organ 4, alternately with the V-bus 9, in absolute value does not exceed 1 the maximum permissible flowing logic unit and the maximum permissible flowing current of the logical zero of the direct output of circuit 1, respectively, but mostly close to these last values. The maximum resistance R,

4 max

organ 4 is such that when R changes from an average value to zero and q K iox, the resistances K and R change in a ratio that is greater than the sum of the maximum possible permissible relative deviations from the nominal values of the capacitor 3 and resistors used in the generator and to the last sum, for example, at ten percent indicated specified permissible deviations s {the nominal maximum resistance of the organ 4 can be chosen equal to the nominal resistance of the resistor

Work pulse generator, in which; Scheme 1 is made in the form of three CMD-logic inverters connected in series 13-15

(Fig. 1), is illustrated using the time synchronous diagrams shown in Fig. 2 for the voltage U., at the input of the circuit 1, which is the input of the inverter 13, for the voltage U, on

the output of the inverter 13, for the voltage at the forward output of the circuit 1, which is the output of the inverter 14, for the voltage UQ in, the connection point 24. between the second terminals of the resistor

5 5 and regulator 4, with the voltage U - U, U acting as the voltage E on the bus 8 relative to the belt 9, for the voltage U on the first face of the capacitor 3

0 relative to its second plate and for current ij through a capacitor, for which the positive direction is taken from the first to the second plate of the capacitor.

To simplify the diagrams, the gains of the inverters 3 and 14 in the middle areas of their output switching characteristics are taken so large that the maximum and minimum values of voltage and, at which the voltage U

five

enters the active region of the switching characteristics of the inverter 14 from above and below, respectively, 5 differ only slightly from each other and therefore are assumed to be equal to one value of the switching threshold U, inverter 13, and that the maximum and minimum voltage values

0 and 25 at which the voltage U enters the active switching area from above and below, respectively, also differ slightly from each other, but therefore are assumed to be equal to one

45 value of the threshold switch U, inverter 12. Moreover, it is assumed that. and .2 U (v, which practically takes place when using as inverters 13 and 14 equally included logic elements included in the same integrated microcircuit. For definiteness, U takes somewhat less than 0.5 E, and for example marriages of zero and single logical

The 55 levels of inverters 13–15 are assumed to be zero and E, respectively.

At the moment of time t, the voltage and, can be both less and more Uj (,. Suppose (fig. 2)

that at time t, U is less and so much that U is greater than U, in this case, U has a value close to zero, and and is a value close to E (the output logic signal of the inverter 15, represented by voltage levels U, is the logical inversion of the output logic signal of the inverter 14, represented by the voltage levels U, in view of this

J

For simplicity, the timing diagram for the voltage U (not shown, and the capacitor 3 is charged with a positive current from the output of the inverter 15 through the circuit 2. When the voltage is entered and from below (on the side of smaller values) to the active region of the switching characteristic of the inverter. 13, the voltage U. decreases from close to E value, rushing to zero value, with a speed equal in absolute value to the product of the rate of change of voltage U by the value of the inverter gain factor 13, which in the middle part of the indicated active region As a rule, it usually reaches its maximum value (in the order of several tens or hundreds).

 When entering the voltage U from above into

the active area of the inverter switching characteristic 14, as soon as the product of the gains of the inverters 13 and 14 and the voltage transfer ratio u reaches the point 24 by the resistive circuit formed by the regulating body 4 and the resistors 5-7, as a result of the positive and positive feedback connection, covering inverters 13 and 14, through series-connected resistor 6, regulator 4 and capacitor 3, at time t occurs regenerative process of switching acceleration of inverters 13 and 14, quickly ending vary: setting at their outputs close to zero and E values of the voltages U.g and Uj, respectively. In this case, the voltage U increases in a jump from., TO U, This jump is transmitted by capacitor 3 to the input of circuit 1, increasing the voltage U, from U to the maximum value U, almost simultaneously, the voltage U jumps from a value close to E, to a value close to zero

value.

The value of U ° is approximately equal to and °: which would have a voltage and and with and broken

1285563

the capacitor circuit 3, how much more U to the ment of time t, the current

namely netak how k mo- i having

 - 1 minimum positive value

i,, creates additional resistance at the output.

o

5 0 5

The value of R o at point 24 is a positive drop. The value of U is approximately equal to the value that would have the voltage U, with U, E

dJ

which

and a broken circuit of the capacitor 3, namely, somewhat less than U.j, since at time t the discharge of capacitor 3 by current i begins, which in moments t of time t takes on a negative value i maximum in absolute value. , Of what

you can see that the value of U

1-1

more and.

no more than the magnitude of the difference; Between the values Ul,. and U °, the latter at the specified choice of resistances of resistors 5-7 does not exceed the difference between E and U, therefore the voltage U at the moment of its positive jump remains less than the value of E (for any established values of resistance R and R).

, thirty

capacitor

From time t

9 is first discharged from a positive charge, and then recharged by a negative current i. In this case, the voltage and decreases exponentially through the resistances R and Rg connected in series with 35 of it. This change in voltage U is accompanied by a decrease in the absolute value of the negative current i, which in turn leads to a slight increase in voltage Uq relative to the value of Ua,. When the voltage and the top reach a value close to Un, at the time t as described for time t, a regenerative process of step-wise reverse switching of the output logic signals of circuit 1 occurs, as a result of which the voltage U is again, and

40

45

50

55

and take values close to E, the voltage U. - close to zero. In this case, the voltage U Q abruptly decreases to the value TJ. close to and, „. This jump is transmitted to capacitor 3 at the input of circuit 1, reducing the voltage U from approximately to the minimum value of U.

Since by the time t current i. negative

i, creates on resistance R., t-. uh

An additional negative voltage drop, slightly reducing the voltage U relative to the value of S at time t, current i taking a positive value ij 2 creates on resistance Rd

additional position voltage drop, slightly increasing the voltage Ug relative to the value

 . l- 3

and

then the magnitude of the negative

voltage jump U, at the moment of time t in absolute value does not exceed the magnitude of the difference between U, ....,

oa

And Ug.xx Lastly, with the specified choice of resistances of resistors 5-7, it does not exceed U, therefore, the voltage remains above zero at the moment of its negative jump (for any set values of resistances R and R).

From the time t, the capacitor 3 is first discharged from a negative charge and then recharged.

Ry. when installing pointer 20 against scale mark 22 and resistance R,

fO for example, the resistance of the resistor 17, when setting the pointer 20 against the scale mark 21, that after this adjustment the pulse generator provides a fairly accurate setting

} 5 using the unit of resistance of circuit 2 of the upper and lower limits of the installation T directly on a scale of 19. As during the operation of the pulse generator at any resistance R. and any established value of resistance R, the voltage remains in the range from zero to E, ; the input impedance of circuit 1 remains very high all the time

positive current i. At the same time, even with protective circuit 1

The stress U increases exponentially through the resistances R and Rg until it again reaches the bottom value jUy. Next, the pulse generator operates in the described manner cyclically, forming on the bus 10 a periodic sequence of rectangular pulses, the period T of which can be set to a certain range in a certain range using the setpoint of resistance of circuit 2 directly on its scale 20. With increasing resistance R ,, from zero to R voltage spikes and at time t ,, t, t ... the value of this voltage reaches. , alternately, from below and from above, decrease from the maximum to the minimum absolute value, with the period. monotonously decreases (with fixed resistance R uenH 2). And with such large values of relations

R

Min

to Rg that take place for

specified range of R

and the specified values, R.,

oh

R

Have

relative changes of T at fixed values of S .. and R., H are approximately the same, i.e. of .vieHeHHe R, generates approximately the same relative changes in the upper and lower limits of the installation. Change the second part of R with

556310

the resistance R, for example, with the help of a resistor 17 has a much stronger effect on the lower than the upper limit of the installation T. Therefore, the pulse generator provides the possibility of such adjustment by alternately selecting the resistance

Ry. when installing pointer 20 against scale mark 22 and resistance R,

For example, the resistance of the resistor 17, when setting the pointer 20 against the scale mark 21, that after this adjustment the pulse generator provides a fairly accurate setting

using the unit of resistance of the circuit 2 of the upper and lower limits of the installation T directly on the scale 19. Since during the operation of the pulse generator at any resistance R. and any set value of resistance R, the voltage remains in the range from zero to E, then; the input impedance of circuit 1 remains very high all the time

Rtsiodov at its entrance.

Since in the pulse generator the input voltage of the threshold logic circuit in the entire adjusting range of its regulator is in the range from zero to E, it excludes the possibility of opening the threshold logic circuit of the basic thyristor structure, which is usually available in SchTsP-integ

logical logic circuits and the opening of which can cause irreversible destruction of the logic circuit. Therefore, the proposed pulse generator has a much higher reliability.

In cases of application of a pulse generator, when a sufficiently accurate period setting is provided and with arbitrarily large values of the resistance of the resistor 7, the latter can be excluded. At the same time, it is necessary to maintain this ratio between the resistances of resistors 5 and 6 in order to ensure reliable operation of the pulse generator.

Claims (2)

1. A pulse generator containing a CMD threshold logic circuit with direct and inverse outputs, a time specifying a resistive circuit, the first input of which is connected {1nen with an inverse output of a CMDP threshold logic circuit, a capacitor, the first plate of which is connected to the second input time a resistive circuit, a resistive adjusting body, the first resistor, the first view of which is connected to the common bus of the pulse generator, the second output - to the second input of the resistive adjusting body, characterized by the fact that the ability to set the pulse following period and increase reliability; A second resistor is inserted in it, which is turned on. t, t, tt t, Composition) ntel N. Ferapontova Editor A. Shishkin Tehred M. Khodanych Proofreader p. Cherni Order 7533/55 Circulation 899 Subscription VNISHI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 between the first input of the regulator and the forward output of the CMD threshold logic circuit, the first capacitor plate is connected to the input threshold logic circuit, the second plate with the second output of the first resistor. 2. The generator according to claim. D, characterized in that, for the purpose of further development. the accuracy of the installation of the pulse following period; a third resistor is inserted in it, which is connected between the second output of the first resistor and the power supply bus of the CMD threshold logic circuit. {put. g