SU1282357A1 - Output stage of frame scan - Google Patents

Abstract

The invention relates to television technology and predicts an increase in the linearity of the output of a vertical scan by reducing the duration of the reverse run of the vertical sweep. During the first half of the forward stroke of the frame sweep, the storage capacitor (NC) 4 is charged from the power source (PI) to the voltage Ug across the circuit: the bias coil 1 - charging resistor 2 - charging diode (DD) 3 - NC 4 - disconnecting diode 5 - common bus. The voltage drop across the AP 3 is applied in reverse polarity to the base-sumitter transition of the switching transistor 6, closing it. In the second half of the forward stroke, when the current in the deflecting coil 1 changes polarity, the NK 4 is charged to the level of 1.5 UB due to the discharge of the coupling capacitor 8 along the circuit: charging resistor 2 - ZD 3 - NK 4 - the disconnecting diode 5 - PI - output transistor 9 - coupling capacitor 8. With the beginning of the return stroke, PD 3 is closed and the switching transistor 6 opens, connecting the NC 4 in series with the PI, the power of the frame output sweep is supplied from a voltage equal to zheny NK 4 and IP, At the end of the reverse stroke HT 3 opens and bypasses the input circuit of the switching transistor 6. Through the open HT 3 HA .chinaet again be charged 4. NK 1 yl. , f (L C

Description

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The invention relates to television technology and can be used in scanning circuits of television receivers and video monitoring devices.

The purpose of the invention is to increase the linearity of the output of the vertical sweep by reducing the duration of the reverse stroke of the vertical sweep.

The drawing shows the basic electrical output-Hort circuit of the vertical scanning cascade.

The frame output stage includes a deflection coil 1, a charging resistor 2, a charging diode 3, a storage capacitor 4, a disconnecting diode 5, a switching transistor 6, a resistor 7, a coupling capacitor 8, the first and second output transistors 9 and 10.

Output stage frame scan works as follows.

During the first half of the forward run of the frame sweep, the storage capacitor 4 is charged from the power source along the circuit: deflection coil 1, charging resistor 2, charging diode 3, storage capacitor 4, disconnecting diode 5, common. The capacitor is charged to the level and equal to the supply voltage. The charge current of the storage capacitor 4, which flows through the charge diode 3, creates a voltage drop across it, which, being applied in reverse polarity to the base-emitter transition of the switching transistor 6, supports. drinking it in a closed state. In the second half of the forward stroke, when the deflection current in the deflecting coil 1 changes polarity, the storage capacitor 4 is charged to a level of 1.5 Ug, due to the discharge of the coupling capacitor 8 along the circuit: charging resistor 2, charging diode 3 , storage capacitor 4f-disconnecting diode 5, power supply, first output transistor 9, isolation capacitor 8. At the same time, charging diode 3 performs the same function g; as in the first half of the forward stroke.

With the beginning of the return stroke

Ug at point B ceases to increase, i.e. will become less in absolute value than the voltage across the storage capacitor 4. ZAR d

The diode 3 is closed and the switching transistor 6 is opened, connecting the storage capacitor 4 in series with the power supply.

At this time, the disconnecting diode 5 is closed, and the output stage cascade is powered from the voltage, which is the sum of the voltages on the cumulative

capacitor 4 and power supply. At the end of the reverse stroke, when the voltage on the deflecting coil 1 begins to increase again and the voltage on the accumulative

the capacitor 4, the charging diode 3 opens and shunts the input circuit of the switching transistor 6. Through the open charging diode 3, the storage capacitor 4 starts to charge again and the process described is repeated.

Claims (1)

Invention Formula Frame Scan Output Cascade containing a deflection coil, The first output of which is connected to the first output of the coupling capacitor, the second output of which is connected to the combined output electrodes of the first and second output transistors, the input electrode of the second output transistor is connected to the first output of the storage capacitor and the first output of the disconnecting diode, the second output of which is connected to the common busbar and with the collector of the switching transistor, the emitter of which is connected to the second output of the storage capacitor and to the first output of the charging diode, the second the output of which is connected to the first output of the charging resistor and the first output of the resistor, the second inference, which is connected to the base of the switching transistor, the input electrode of the first output transistor, is the input voltage of the first and second output transistors are inputs of a frame deviation signal, characterized in that, in order to increase the linearity of the output signal, a frame sweep by reducing the duration of the return stroke of the frame sweep, the second terminal the deflecting coil is connected to the input electrode of the first 312823574 output transistor, and the second you-point of connection of the deflecting coil the water of the charging resistor is connected to an isolating capacitor.