SU1259517A1 - Synchronizing signal generator - Google Patents

Abstract

The invention relates to television technology. Synchronization time is reduced when the input video signal is changed. The device contains a controlled rr 1, a pulse counter 2, 3, a signal driver 4, a synchroseptor 5, a phase detector 6, a low-pass filter 7, a phase comparator 8, a key 9. The goal is achieved by introducing an RS-trigger 10, keys P, 12, storage unit 13. Comparator 8 contains a 0-flip-flop, .RS-flip-flop, element And and trn pulse maker. After the video signal has been changed at the input, the phase time AFC system, formed by Mr. 1, phase filter 6 and low pass filter 7, does not experience sharp drops, which favorably occurs at the time of its establishment, at 1 hp. f-ly, 2 nl. (L 1C ate with cl

Description

I

The invention relates to television technology and can be used in the receiving part of various television systems, including television measurement equipment.

The purpose of the invention is to reduce the time in the farm to synchronize when changing the input video signal.

FIG. Figure 1 shows the structure of the electrical circuit of the synchronous generator; in fig. 2 is a structural electrical circuit of a phase comparator.

The sync driver (Fig. 1) contains a controlled oscillator (UG) I, the first 2 and second 3 pulse counters, the shaper 4 signals, the synchro selector 5, the phase detector (PD) 6, the low-pass filter (LPF) 7, the phase comparator (FC) 8, first key 9, RS-TpHrrep 10, all key II, third key 12, storage unit 13

While FC 8 contains (Fig. 2) 0-flip-flop 1A, RS-flip-flop 15, the element And 16, the first 17, the second 18 and the third 19 pulse shapers,

Sync generator works as follows.

 In the steady state, signals from a UG 1 signal phased with the sync pulses of the input video signal form signals with a frequency of lines and frames, the phase of which is also rigidly connected with the input video signal. Counter 2 pulses signal UG 1 is divided to the line frequency, and counter 3 - to the frame rate. The formation of the signals of the required fori 1 is carried out by the Shaper 4 signals. For the operation of the phasing circuits of sync selector 5, frame sync pulses are made from the input video signal, phasing the counter 3, as well as the horizontal small pulses used for the operation of the CTOTt phase-locked loop (PLL), formed, except for UG 1, in blocks PD 6 and LPF 7. At the same time, the FC 8 locking synchronous operation of the synchronous generator, holding the key 9 in a closed state, also resets the RS trigger 10, the output of which switches the keys 11 and 12 so that the output of the LPF 7 comes to HS inputs 1 and memory unit 13.

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In the case of switching the video signal at the sync generator RS-trigger 10, the switching signal arrives from outside, the second AND and third 12 keys switch, causing the input of the storage unit 13 to be disconnected from the output of the low-pass filter 17, and the output of the storage unit 13 is connected to the input of UG 1 which begins to form a fixed frequency signal. At the same time, FC 8 unlocks key 9 until the horizontal sync pulses of the INPUT video signal coincide in phase with the internal sync pulses from the output of the imaging unit 4. As soon as the FC 8 detects the synphasm of these signals, the key 9 closes and resets the RS-flip-flop 10. t. e. the synchronous generator proceeds to work in the slave mode with minimal mismatch, thus achieving rapid synchronization entry.

FC 8 works as follows.

With proper phasing of external and internal sync pulses, when external sync pulses are slightly ahead of internal ones, 0- TRIGGER 14 is constantly in a single state. In this case, the signal from its inverse output blocks the passage of the signal from the output of the RS flip-flop 15 through the element 16 to the control input of the key 9. When switching the input video signal due to the absence of an external sync pulse at the right moment, the RS flip-flop 15 is set to the zero state. In the interval between the leading edge of the inner and the falling edge of the external sync pulses (the fronts are allocated by the shaper 19 and 18, respectively), the output of the RS flip-flop 15 is high and the voltage level that switches the key 9 through the AND 16 element. are phased in the described manner, the O-flip-flop 14 is again transferred to the one state, while the shaper 17 generates a short pulse to reset the RS flip-flop 10, and the And 16 element is again blocked.

Thus, after changing the video signal at the input of the sync generator, the FAICH system does not experience sharp

rolls, which favorably affects the time of its establishment. If it is necessary to block the output signals of the synchronous generator for the duration of the transition process, a prohibition block may be turned on at the output of the synchronous generator, controlled by the signal e of the output of the RS-trigger 10.

Claims (2)

Invention Formula I, a synchronous generator containing a serially connected control generator, a first key and a first pulse counter, the bit outputs of which are connected to the first group of inputs of the signal generator, the outputs of which are the outputs of the clock generator, the second group of inputs connected to the bit outputs of the second pulse counter, whose counting input is connected to the high-order output of the first pulse counter and to the first input of the phase detector, and the installation input is connected to the first output of the sync selector, whose input It is the video signal input, and the second output is connected to the first input of the phase comparator and to the second input of the phase detector, the output of which is connected to the input of the low-pass filter, while the second input of the phase comparator is connected to the output of the horizontal sync pulses of the signalformer, and the first output is connected to the control the first key input. five five 0 five 0 characterized in that, in order to reduce the time of occurrence of B synchronism when changing the input video signal, the second and third keys, a storage unit and an RS flip-flop are entered, the first input of which is. is the input of the switching signal, the second input is connected to the second output of the phase comparator, and the output is connected to the control inputs of the second and third keys, the combined signal and first signal inputs of which are connected to the output of the low-pass filter, the output of the second key is connected to the second key the signal input of the third key, the output of which is connected to the input of the controlled generator, 2. The clock generator according to claim 1, characterized in that the phase comparator contains three pulse drivers, an RS flip-flop, a 0 flip-flop and an AND element, the output of which is the first output of the phase comparator, the first input connected to the output of the RS-flip-flop, and the second input is the inverse output of the 0-flip-flop, the direct output of which through the first form1 rotor-impulse OB is connected to the second output of the phase comparator, the first and second inputs of which are respectively the information and clock inputs of the D-flip-flop, respectively connected via the secondthird pulse shapers with the first and second inputs of RS-flip-flop, hpc tnS Compiler L.Stasenko Editor M.Blanar Tehred I.Popovich Proofreader V.Si nicke Order 5141/59 Circulation 624. Subscription VNIIPI USSR State Committee Inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab, d. 4/5 Production and printing company, Uzhgorod, st. Design, And