SU1254488A1 - Device for monitoring and diagnostic checking of digital units - Google Patents

Abstract

The invention relates to the field of automation and computing: to devices for monitoring the performance and searching for defects in discrete nodes and blocks. The purpose of the invention is to expand the functionality by providing control over circuits and discrete blocks containing combinational circuits and memory elements. The device contains a test memory block, a memory block, a comparison block, a malfunction site analysis block, a control block, a switch, an address registration block and a display block. In the first diagnostic mode, combinational circuits are checked, and in the second, sequential circuits, the same as the memory elements, are checked. The forwarding mode is provided when a defect is entered. The addresses of test sets and the defect numbers are automatically recorded, 10 Il. with S (L

Description

The invention relates to automation and computing: to devices for monitoring performance and searching for defects in discrete nodes and blocks.

The purpose of the invention is to enhance the functionality by providing control over circuits and discrete blocks containing combinational circuits and circuits containing memory elements.

FIG. 1 shows a device diagram} in FIG. 2 is a control block diagram; in fig. 3 is a diagram of the failure location analysis unit f in FIG. 4 is a diagram of an address registration unit in FIG. 5-8 The algorithm of operation of the device in FIG. 9 is the type of defect detection test for the diagnostics mode (and the combinational circuits, the first mode b - sequential circuits, the second control mode); in fig. 10 is an example of a defect finding test for circuits containing elements.

memory I

The device (Fig. 1) contains a test memory block, a memory block 2, a switch 3, a comparison block 4, an indication block 5, a control block 6, a monitored discrete block 7, a fault analysis block 8, an address registration block 9.

 The control unit (Fig. 2) contains a register of 10 micro-instructions, a register 11, a start input 12, a device bypass input 13 for detecting defects, the ninth element OR 14, the first element OR 15, the fourth element ШШ 16, the fifth element OR 17, the third element SH-18, seventh element OR 19, sixth element OR 20, eighth element OR 21, second element OR 22, seventh element AND 23, third element AND 24, fourth element And 25, tenth element AND 26, sixth element And 27, the first element And 28, the second element And 29, the eighth element And 30, the fifth element And 31, the ninth element And 32, the seventh element 33 delays, the first delay element 34, the fourth delay element 35, the third delay element 36, the sixth delay element 3.7, the eighth delay element 38, the second delay element 39, the fifth delay element 40, the third NO element 41, the first NO element 42, the second

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element NOT 43, trigger trigger trigger 45.

The malfunction location analysis block (Fig. 3) contains an address memory block 46, a number register 47, a test word current address counter 48, a defect number counter 49, a comparison circuit 50 and 51, an OR element 52.

The address registration block (FIG. 4) contains a group of shift recorders 53.

The test memory block is intended for storing test sets received at memory block 2, as well as command information received at the control flea 6.

The memory unit 2 is intended for storing and delivering a test test through the switch 3 to the unit under test, and the reference reaction to the group of inputs of the unit 4 of the comparison.

Switch 3 is designed to connect the outputs of block 2 of memory 5 to the inputs of the tested block 7, and the outputs of the tested block 7 to the input of block 4 of the comparison.

The control unit 6 is designed to generate: control information on the test memory block for organizing its operation / on memory block 2 — a signal for enabling the test set to be supplied through switch 3 for a test block 7} for a comparison block 4 — a reference signal for comparing the reference set and received responses; on the display unit 5 - the indication resolution signal to the fault analysis unit 8 - information for organizing its operation on the address registration block 9 - zero signal, recording resolution and information shift

The malfunction location analysis unit 8 is designed to generate test set numbers entered in the registration block 9 of addresses of the number of the class of equivalent defects entering the display unit 5 (signal of comparison or comparison of the address of this test set with the address of the next test set analyzed entering block 6 control in forwarding mode.

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Unit 9 of registration of addresses is intended for storing and issuing test addresses to block 5.

sets, which was the comparison of the reference and the resulting reactions.

FIG. 2 accept the following designations as applied to the outputs of the gistra microinstructions (see also Fig. 9a): CG - group of outputs of the sign of the inputs (outputs controlled by the MU discrete block, switching test)} CCW - output of the sign of the end of the switching test of the microinstructionsJ TH - test set J KTNO - the output of the sign of the test set cone (T) under the control of combinational circuits of the register of microcommands J OTN - area TN, includes test set (T) and TTH (end of test sets) | KID - output sign of the end of the control register 10 micro-commands; KPRM - mark the end of the test instructions; OID - identifier area, includes TH, KTNO, OT, KID, KPRM, KTPDO, KTPDO - the output of the sign of the end of the defect finding test in the mode of control of combinational circuits of microcommands.

To search for defects in the diagnostics mode of sequential circuits containing memory elements, designation marks (Fig. 2 and 96): KNU - output of the sign of the initial setup of the register of micro-commands KTH 1 - output of the end of the test set in the diagnostics mode of the circuits, holding elements of memory; OTI - TI area, includes TI and KTI1, OL - area includes TN, KNU, KTN1, OTN, KTPD1; КТЦДД1 is the output of the sign of the end of the defect search test in the defect search mode of discrete block circuits containing memory elements of the microcommand register.

The device (Fig. 1,5-8) works as follows.

The signal applied to the start input 12 from the control unit 6 is used to prepare the malfunction site analysis unit 8 and the address registration unit 9. Then, from the output of the element OR 15 of the control unit 6 from the test memory block 10, the register of 10 microcommands; control unit 6 reads the switching test (CT), which through register 11 enters the control inputs of switch 3 which produces

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leads the required commutation of the external contacts of the tested discrete block 7 to the outputs of the memory block 2 and to the input group of the comparison block 4. The device can operate in two modes: the first is the search for defects in discrete blocks without memory elements (combinational circuits), the second is the search for defects in discrete blocks with memory elements (sequential circuits). Therefore, the further operation of the device will be considered in two modes.

The control unit 6 (Fig. 2.5-8) operates as follows.

The defect search is initiated by sending a high level signal to the start 12 input. As a result, firstly, the start trigger 45 and the control trigger 44, the address registration block 9, the current address address word test counter 48 are set to zero and the defect class number counter 49 through the OR element 22, secondly, two signals are generated : through the element OR 15 - signal THB - permission to output information by the test memory block 1 and the DCB signal - a recording of the switching test (CT), which allows the transmission of CT from the memory block of tests through the register of 10 microcommands to the register 11. From the register 11 CT supplied to switch 3. CT contains t information input and output pins is checked emogo unit 7, according to which the switch 3 podklk - chaet input terminals to the output memory unit 2, and the output of the group Contacts- unit 4 inputs the comparison. When reading a CCP tag recorded at the end of the CT scan, the register of micro-instructions 10 causes the corresponding CCP signal, which, firstly, through the AND 23, OR 20 elements increases by one the contents of the counter of the defect class number 49J secondly, generates two signals: the THU signal through the element OR 15 and the TLV signal, the writing of the test set through the element OR 16, which allows reading and transmission of the test set (TH) from the memory of test 1 to the memory 2.

Further operation of the control unit 6 will be considered in two modes of the device operation under the control of circuits and sequential circuits.

Combination schemes. On the signal of ECHL O and SCN - O in the analysis block

the location of the fault is determined by the number of the first class of equivalent defects. Then, the signal from the output of the element OR 15 records the first test set in memory block 2 and the reference reaction corresponding to the response of the tested block 7 in the presence of a defect of this class. The test set from memory block 2 through switch 3 is fed to the input of the tested block 7. The response of the tested block 7 through the switch 3 is fed to the input group of the compare block 4. At the same time, the reference reaction is fed to another input of the comparator unit 4 from the memory unit 2. If the reference and received feedbacks do not match, the comparison unit 4 generates an incomparability signal that goes to the open elements AND 24 and 25, the NOT element 43. The occurrence of the noncomparison signal indicates that there are no defects of this class in the checked block 7. In this case, the control unit 6 issues a command to the fault location analysis unit 8 to set the number of the next class of equivalent defects and a command to the test memory block to go to check the next Identifier, after which the actions are checked. In the case of the absence of a signal of incomparability from comparison unit 4, after a time equal to the diagnostic cycle, control unit 6 issues a command to enter the next test set of the given identifier. If the checked block 7 was already checked on all sets of this identifier, and the incomparable signal did not follow, then in the checked block 7 there is one of the defects of the corresponding defect class Control block 6, determining the end of the identifier when trying to read the next test set, issues a command to block 5 of the diction to indicate the class number

defects coming from block 8 analysis of the location of the fault. By the defect class number, the defect is cleared and the defect is eliminated. Then, the operation of the device is repeated until all defects of the tested block 7 are completely eliminated. If the defect search test has passed to the end, then in the display unit 5, a zero number is indicated.

defect class, which corresponds to the absence of defects in the checked block 7.

Sequential circuits. By command, from the control unit 6 from the test memory unit 1, a test set is written to the memory unit 2, which is intended for the initial installation of the tested unit 7 and which through

0, the switch 3 arrives at the input of the tested bock 7, transforms the block 7 to the initial state. After that, by a command from the control unit 6 in the fault analysis unit 8

5 sets the address of the first test suite. Then, at the command from the control unit 6 from the test memory unit 1, a test set and a reference set are written to the memory unit 2.

0 reaction, corresponding to the reaction of block 7 in the presence of a defect in it from the classes of defects found on this test set. The test set from memory block 2 through commutator 3 is fed to the input of the tested block 7. The response of the tested block 7 through the switch 3 is fed to the group of inputs of the 4 comparison block. At the same time

0 another group of inputs of block 4 comparison from memory block 2 is received

. reference reaction. In the case of a mismatch of the reference and the received responses, the comparison unit 4 through the time, the diagnostic response peaks, generates a signal: incomparison, which -: - that goes to control unit 6. The appearance of the signal of incomparability indicates that in the tested block

- 7 there are no defects from the classes of defects found on this

test set In this case, following a command from the control unit 6 from the test memory unit 1, the next test set is written to the memory unit 2, and the operation of the device is repeated on this test set.

In the case of the absence of a signal of incomparability from block 4 comparison, after a time equal to the diagnostic cycle, control block 6 outputs the command for which from the block of analysis of the fault location to block 9 of registration. addresses are recorded on this test set. In addition, the device is put into forwarding mode.

The need for this mode is explained by the fact that in this test

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In the general case, several classes of defects are found. In order to isolate the class of defects that are actually present from among the suspects, it is necessary to compare the responses only on those test suites that, together with this test suite, form identifiers for all defect classes detected on this test suite. The addresses of these test cases form a chain of addresses, which is stored in block 8 for analyzing the fault location. Then, the command from the control unit 6 in the fault location analysis unit 8 sets the address of the next test set to be analyzed (MF + 1) and reads the next test set from the test memory unit 1 to the memory unit 2.

If the address of this test set is not equal to the address of the next set to be analyzed, then block 8 generates a noncomparison signal, which goes to control block 6 and reads the next test set ri operation of devices on this test set. .

If the address of the next test suite is equal to the address of the next test suite being analyzed, the failure place analysis unit generates a comparison signal, which will go to the control unit 6. On this signal, the control unit 6 allows the comparison in the reference unit 4 of the reference and response reactions. In case of a mismatch between the expected and received responses, the comparison unit 4 generates a non-comparison signal, which is fed to the control unit 6. On this signal, control unit 6 generates a command to block 8 dl. performing the redirection cycle and a command to the test memory block t for reading and writing to the memory block 2 of the next test set in which the operation of the device is repeated. If there is no incomparable signal from the comparison unit 4, after a time equal to the diagnostic cycle, the control unit 6 issues a command to the address registration unit 9 for recording from the analysis unit of the location of the address malfunction of this test set, the command to the analysis unit 8 for the location of the failure

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Perfection of the redirection cycle and the command to the test memory block 1 for inputting and writing to the memory block 2 of the next test set, at 5 which the operation of the device repeats. If the defect detection test has passed to the end, then the control unit 6 issues to the indication unit 5 an indication display address resolution test command set, which comes from the address registration unit 9 and on which the expected and received reactions have been compared. These numbers determine and eliminate the defect in the tested block 7.

Combination schemes. The test memory block 1 through the register 10 generates the corresponding signal of the CTLO, which comes, firstly, through the element 20 OR 17 (CONT1 signal) to the memory block 2 and allows the flow of the voltage transformer to the checked block 1 secondly, after the time has elapsed equal to the response set at the output of the checked block 7 and determined by the delay element 34, the KONT2 signal enters the comparison block 4 and allows the comparison of the reference reaction recorded in block 2 of the reference reaction and the response reaction from the checked block 7j

thirdly, through the delay elements 34 and 39, to the input of the element AND 27, and prepares a path for passing the signal of non-comparison of NCPB through the element AND 27. The delay element 39,

calculated at the time of the comparison of reactions, designed to eliminate the false positives of the element And 27. The result of the comparison can be

Q is double, therefore we consider both cases.

When the response coincides with the expected signal NSSR from block 4 comparison is missing. In this case, a unit is present at the output of the HE 41 element, and at the instant of time determined by the delay element 39, permission 27 is given to the memory block 1 through the AND 27 element.

0 tests and submission to block 2 of the memory of the next TN.

If the response does not match, then the NCPB signal is transmitted from the comparison unit 4 to the control unit 6. This signal passes through the element And 24 and, firstly, the output of the element NOT 41 sets a zero, which prohibits the reading

next TN, secondly, in the test memory block 1, the PFP addressing signal to the cell, where the CPRM label is stored, is stored. The need for this is due to the fact that as a result of the non-coincidence of the reactions, the absence of defects from this class is proved, which means that it is not necessary to submit the remaining TI identifier.

The test memory block through the register of 10 micro-commands vtsdaet the corresponding signal CPRM, which provides actions similar to those of the CCT signal. The test memory block 1 generates a CID signal — the end of the register identifier 10, from which it enters the display unit 5 through the ENENT or 14 and enables the display of the number of the class of equivalent defects (CED) from the fault analysis unit 8 .

After elimination of the found defect, the search for defects can be. continued with high potential input to device 13. As a result, through the element OR 15, the test memory unit receives a signal THU, which reads the CPRM label, and the resistor 10 outputs the CPRM signal.

If the defect detection test has passed to the end, i.e. the CTPDO label is read, through the corresponding section of the register 10, the CETA signal will be received, which, first, through the OR element 22 enters the malfunction site analysis unit, wraps the defect number counter 49; secondly, through the OR element 14 enters the display unit 5 and enables the indication of the zero number of QED received from the fault analysis unit 8. The zero number of the QED indicates the absence of QED of the checked block 7 and the end of the search for defects.

Sequential circuits. If the test memory block 1 contains a label in the set, the CIA is the end of the initial setup, this signal first sets the control trigger 44 to one, i.e. switches the device to the QED search mode in serial circuits; secondly, through the OR element 22 it enters the fault location analysis unit 8 and zeroes the defect number counter 49,. sets a zero number; third, increases by one the contents of the counter 48 of the current address

Fourthly, through the element OR 17, the CONTT signal enters memory block 2 and allows the flow of the voltage transformer to the checked block 7, according to which the latter is set to the initial state fifth, a sufficient time for. setting block 7 and determined by delay element 33, through delay element 33 it generates permission to read the test memory block and transfer to the memory block 2 of the next TH.

With the arrival of the label KTN1 from block 1 through the register 10, this signal KTN1, first, through the OR element 20 enters the block of analysis of the fault location and increases by one the contents of the counter 49 of the defect number, i.e. sets the number of the supplied THj in the second, through the delay element 36 is fed to the inputs of the elements And 28-30. The passage of the KTHN1 signal through one of the AND 28-30 elements is determined by the state of the trigger trigger 45. Therefore, the further operation of the control unit 6 will be considered in two modes: sequential analysis of the TH (start trigger 45 is in the zero state) J redirection (start trigger 45 is in the single State).

If start trigger 45 is in the zero state, then the KTH1 signal goes, first, through the AND 30, OR 19, 17 elements (KONT1 signal) to the memory block 2 and allows the supply of one TN to the tested block 7; secondly, after a time equal to the response at the output of the checked block 7 and determined by the delay element 35, through the elements 30, ШШ 19, the delay 35, OR 18 the signal of the COIL2 in the reference reaction and response from the tested block 7; Thirdly, through the delay elements 35 and 40, it arrives at the input of the And 31 element and prepares the path of the HCPB signal from the comparison unit 4 through the And 31 element. The delay element 40 is designed for the comparison time of the reactions. And it is intended to eliminate the false positives of the And 31 element. The comparison result may be double, so consider both cases.

If the response does not match the expected response, then from block 4 of the comparison, in block 6 of the control signal

one

NSRB This signal passes through elements 25 and 26 and generates permission to read from memory 1 of the test memory and transfer to memory 2 of the next TN.

If the response reaction coincided with the reference one, then the NCPB signal from block 4 of the comparison is absent. In this case, a unit is present at the output of the HE element 43, and at the moment of time determined by the delay element 40, a single signal appears at the output of the AND element 31, which first sets the trigger trigger 45, i.e. switches the control unit 6 to the forwarding mode; secondly, it enters the address registration block 9 and permits the entry of the address of the TN supplied from the fault analysis analysis block 8} thirdly, after the time required to record the address of the TH in the address registration block 9 and determined by delay element 37, it enters the address registration block 9 and resolves the information shift fourth, through the delay elements 37, OR 21 it enters the fault location analysis block 8. and selects the address of the next TH, which needs to be compared between the reference and the received of the checked block 7 reactive {fifth, after the time required for changing the address in the malfunction analysis block and determined by delay element 38, through delay elements 37, OR 21, delay 38, it generates permission to read memory 1 tests and transfer to memory block 2 of the next TN.

If the start trigger 45 is in unity, the passage of the KTH1 signal through the elements 28 and 29, is determined by the presence or absence of an HCPB signal from the failure position analysis unit 8. Therefore, the further operation of the control unit 6 will be considered in two modes: the required TN has not yet been found (the HCPB signal is present) J the desired TH is found (the HCPB signal is absent).

If the HCPB signal from the fault location analysis unit 8 is present, then the KTH1 signal from the output of the delay element 36, calculated for the time required for the HCPB signal in the 8th analysis block, is

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 This fault passes through the AND 28 element and permits the reading of the test memory block 1 and the submission of the next TN to the memory block 2. If the HCPB signal from block 8 is absent, then the KTHt signal passes through elements AND 29, OR 19 and provides the indicated actions by signals KONT1, KONT2 compared to the reference reaction written in block 2 of the test unit 7 The result of the comparison may be double, so consider both cases.

If the response does not match the expected response, then the NCPB signal is transmitted from the comparison unit 4 to the control unit 6. This signal comes first, through the elements AND 25 and 32, OR 21 to block 8 and selects the address of the next TH, at which it is necessary to make a comparison of the reference and received from the tested block 7 reactions; secondly, after the time required for changing the address in block 8 and determined by delay element 38, through elements 25 and 32, 21, delay element 38, it generates permission to read the test memory block and transfer to memory block 2 TI memory of the next TN. If the response reaction coincides with the expected response, then the indicated actions are performed.

If the test set contains the TFCA tag, then through the register 10, the KTPD1 signal enters the display unit 5 and enables the indication of the addresses of the terminals where the tests received from the address registration unit 9 were compared during the defect finding test.

The operation of the control unit 6 in the sequence defect search mode can be repeated by applying the Start to input 12 signal.

The operation of the malfunction analysis block 8 (Fig. 3) begins with the resetting of the counters 48 and 49, as well as the register 47 according to the signals of the control center 6, respectively, SCLO and SCCHO QT. We will consider further work in two modes: combinational and sequential schemes.

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In the mode of the COP on command from the block 6 of the control of the CCN h - 1 counter 49 produces the current class number

equivalent defects and brings it to the display unit 5.

In PS mode, according to commands from control unit 6, SCL + 1 and ScCHN + 1, counters 48 and 49 form the current address of the test set being analyzed and transfer it to the inputs of the comparison circuits 50 and 51, respectively, which, in turn, 5 together with the element OR 52 forms a non-comparison signal NCPB for output to control unit 6. The first input of both comparison circuits receives information from register 47. Updating information in address register 47 occurs during the redirection cycle, when the control signal from control unit 6 at the address of the current test set formed by the contents of counters 48 and 49 is read into register 47 from the memory block 46, however, during the redirection cycle, the contents of both counters 48 and 49 enter the address registration block 9 for recording and subsequent display in the display block 5.

The operation of block 9 (Fig. 4) begins by resetting all registers 53 by the SET signal O of the Control unit 6. Then, in the redirection cycle, the address of the test set, which compares the reference reaction with the expected, is received in a parallel code from block 8 and is written to the lower bits of all the registers 53. Then the control block 6 raises the ADV signal, which gets to the control input of all the registers 53 and shifts the information from the lower bits to the higher ones, which allows you to save all the addresses of the test kits, in which there was a reference comparison with the expected response. All information from block 9 at the end of the device operation in the PS mode is indicated in block 5 of the indications I. ..

FIG. 10 shows an example of a defect finding test for a sequential circuit. The test consists of 6 rays. Rays follow the test in order of increasing numbers. The points of intersection of the rays and vertical lines (Fig. 7) are double-numbered, for example, on beam 1 there are two points 1-4 and 1-8, in whose designation 1 is the number of the beam, 4, 8 are the numbers of test sets. At the same time, 1-4 and 1-8 are different addresses of two test sets. Consider two examples.

Suppose that for a KEL Kj, on a given set of rays in a test, a k-identifier is constructed, which corresponds to a set of TH addresses: 1-4, 3-5, a. for CAL K ,, a k-identifier is constructed, which corresponds to a set of TH addresses: 1-8, 4-7. As seen,

both of these identifiers do not contain identical TN addresses. Suppose also that they do not contain identical addresses with any other k-identifier in the test. The chains of addresses of all identifiers are stored in memory block 46. At the same time, in order to exit the test, every chain closes a dummy address 7-6, the value of which is greater than the maximum real address 6-12.

Before obtaining the first comparison from the comparison unit 4, the device sequentially analyzes the response of the tested block to the TH with addresses 1-1, 1-2, etc. If available in verifiable

The block of defects from QED on KG on TH with address t-4 produces a signal comparing the response with the expected one. After that, the installation of the forwarding mode in the device and instead of sequential

analysis of reactions to TN in order of increasing their addresses, analyzes of reactions to TH on the address chain. Thus, after receiving a comparison signal on a TH with address 1-4 instead of analyzing the next stage of a response to a TH with address 1-5, the response to a TH with an address that is determined in the following way will be analyzed: in the redirection cycle at address 1-4 from the ROM 46 in the address block 8, the address of the transition 3-5 is read, and the address 1-4 is stored in the block 9 of the registers.

After the TN with this address is located on the punched tape, it is fed to the tested block 7 and, since the block contains defects from QED K, a comparison signal is again formed and a new redirection cycle is organized. As a result, at address 3-5 of the ROM 46, a dummy address 7-6 is read, and address 3-5 is stored in block 9 of registers. Next, the device, when trying to read a test set with the address 7-6, from a punched tape, reads the KTPD1 label. Since in the mode of transfer

Records, when receiving a comparison signal, the corresponding addresses from the strings are stored in the register block, then reading the TFC1 label leads to an indication of the following contents of the register block: t-4, 3-5. At these addresses we determine and eliminate the cd.

Let for KED Kg a k-identifier is constructed, which corresponds to a set of TH addresses: 1–4, 3-5, and for QED Kj, a 1c is constructed — an identifier to which corresponds to a set of TN addresses: 1–4, 1-8, 4-7. As you can see, both of these identifiers contain the first one and the same address 1-4. Suppose also that they do not contain the same address with any other k-identifier. If there are defects in QED K, or K on TH with address 1-4, in the block under test, a signal is generated comparing the response with the expected one. After that, the device sets the forwarding mode in the device and, instead of a sequential analysis of the reactions to TN, in order of increasing their addresses, the responses to the TN along the address chain are analyzed. However, unlike the first example, to eliminate the ambiguity of transitions in chains 1-4, 3-5, and 1-4, 1-8, they organize a chain 1-4, 1-8, 3-5, 4-7, 7 -6, which is obtained by combining the strings of both identifiers.

Thus, after receiving a comparison signal on a TH with address 1-4, instead of analyzing the next step, the response to TH with address 1-5 will be analyzed; the response to the TH with the address, which is determined in the following way: in the redirection cycle at address 1–4 from the ROM 46 in block 8, the address of the transitions 1–8 is read, and the address 1–4 is stored in the register block. After the TH with the address 1-8 is located on the punched tape, it is submitted to the tested block 7 and the response is analyzed. Moreover, the result can be binary. Consider both options.

There was a comparison of the response with the expected. As a result, a new redirection cycle is organized and at address T-8 from ROM 46 in block 8, the address 3-5 is read, and address 1-8 is remembered in block 9. Let

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On the TH with address 3-5, the HCPB B signal is generated by block 4 of the comparison. Since the device is already operating in the redirection mode, a new redirection cycle 5 is being organized, as a result of which the address 46 is read from the ROM 46 at address 3-5. However, due to the presence of a HCPB signal from comparison unit 4, the address 3-5 is not memorized in block 9 of registers. Let the reactions with the address 4-7 be compared on the TN, as a result of which the dummy address 7-6 is read from the block 46 at the address 4-7, and the address 4-7 is remembered in the block 9. When you try to find the TN with the address 7 on the tape 6, the control unit 6 determines the TFC1 label, which leads to an indication of the contents of the register block, i.e. 1-4, 1-8, 4-7, by which Kj is determined and eliminated.

There was a non-comparison of the response with the expected. In addition, in block 4 of the comparison, the HCPB signal is generated. Since the device is already operating in the redirection mode, a new redirection cycle is being organized, as a result of which the address 3-5 is read from memory block 46 at address 1-8. However, due to the presence of a HCPB signal from block 4 of the comparison, the address 1-8 is not remembered in block 9. Let the response with the expected response be compared to the address 3-5, resulting in the address 3-5 being stored in the forwarding cycle in the block 9, and the address 46 is read from address 46 in address 3-5. Suppose that on the TN with the address 4-7, unit 4 of the comparison generates a NCPB signal. Then, at address 4-7, from the ROM 46, the fictitious address 7-6 is read, and the previous address 4-7 in block 9 is not remembered. Thus, when reading the KTPD1 tag, the contents of the block of registers 1-4, 3-5, which is used to identify and eliminate K, are indicated.

Claims (1)

Invention Formula A device for monitoring - and diagnostics of discrete blocks, containing a test memory block, a memory block, a comparison block, a fault analysis block, a control block and a switch, the control block contains a register, with the first output 17 the control unit is connected to the synchronization input of the comparison unit; the uncompression output of which is connected to the first input of the logic conditions of the control unit, the second output of which is connected to the recording input of the memory unit, the group of information inputs of which are connected to the output group of the test word characteristic of the test memory unit, input of word read permission for inputs (outputs), input for input, read permission for the next test word and address input tags, the end of the test set of the test memory block is connected to the third fourth, fifth and sixth outputs of the control unit; the seventh, eighth, ninth, tenth and eleventh outputs of which are connected to the first, second, third, fourth and fifth inputs of the analysis unit fault points, the first output of which g is connected to the second input of the logic conditions of the control unit, the group of inputs (outputs) of the terminal of which is connected to the group of inputs (outputs) of the diagnosed discrete block, while the failure point analysis block contains the first hem comparison, number register, the output group of the sign of the current address of the test word of which is connected to the first group of information inputs of the first comparison circuit, in which, in order to expand the functionality by providing control of discrete blocks containing combinational circuits and circuits containing elements memory, it contains the address registration block, the display block, and the block of the current address of the test word, the counter but the measure of the defect, the second circuit with Equal to the OR element and the memory block of addresses, the summing input of the defect number counter is connected to the seventh output of the control unit, the eighth output of which is connected to the count input of the address memory block, the output group of which is connected to the group of information of the current address which are connected to the second group of information inputs of the first comparison circuit. t ten 15 20 , e-, 1254488 the output of the incomparability of which is connected with the first vhbdom element. OR, the second input of which is connected to the output of non-comparison of the second circuit comparing 5, the first ti of the second group of information inputs of which are connected to the group of discharge outputs of the defect number counter and the group of outputs of the defect number sign in the current test word of the registers, respectively, the bit outputs of the counter of the test address of the test word and the group of outputs of the counter of the defect number are connected with the first and second groups of information inputs of the address registration block, and the group of the bit outputs of the counter When the current address is connected to the first group of information inputs of the display unit, the reset inputs for the current address address of the test word and the defect number counter are connected to the tenth and ninth outputs of the control unit, 25 the summing input of the current test address address counter is connected to the eleventh output of the control unit, output element OR is connected to the second input of the logic conditions of the control unit, the output of which is connected to the group of control inputs of the switch, the twelfth, thirteenth and fourteenth out control unit dyes are connected to a reset input, a synchronization input, and a write input of the address registration block, respectively; the fifteenth and sixteenth outputs of the control unit are connected to the information inputs of the display unit, the second group of information inputs of which are connected to the output group of the address registration block; a test memory is connected to a group of inputs of a logical operation, a control unit; a group of outputs of a test feature of a test memory unit is connected to a group of informs switch inputs, the output group of which is connected to the first group of information inputs of the comparison unit, the second group of information inputs of which are connected to the output group of the characteristic of the reference response of the memory unit, the enable input of which is connected to the trigger input of the device; . ) - 35 40 50 55 nineteen trigger trigger, control trigger, nine OR elements, eight delay elements, three NOT elements and ten AND elements, the group of information inputs of the microcommand register is connected to the input group of the logic operation of the control unit, the first input of the logic condition of which is connected to the first input of the first element And through the first element NOT - with the first input of the second element AND, the second input of the logical condition of which is connected to the first inputs of the third and fourth elements AND and through the second element NOT to the first input n m And, the start input of the control unit is connected to the third output of the control unit, the first input of the first OR element, with zero start trigger and control trigger inputs, with the first input of the second OR element, with the ninth and twelfth outputs of the control unit, the first output of which is connected with the output of the third OR element, the first input of which is connected to the output of the first delay element and through the second delay element to the first input of the sixth AND element, the output of which is connected to the second input of the first OR element and the first input ohm of the fourth OR element, the output of which is connected to the fifth output of the control unit, the second output of which is connected to the output of the fifth OR element, the first input of which is connected to the output of the end sign of the test set for controlling combinational micro-command register circuits and the input of the first delay element the outputs of the signs of the inputs (outputs) of the register of micro-instructions are connected to the group of information inputs of the register, the group of outputs of which is connected. It is not connected with the group of outputs of the control unit, the output of the sign of the end of the switching test of the microinstruction register is connected to the first input of the seventh AND element, to the second input of the fourth OR element, and the third input of the first OR element, the output of which is connected to the fourth output of the control unit, the sixth output with the release of the third element And through the third element is NOT - with the second input of the sixth element And, the output of the sign of the end of the test set in the diagnostic mode elements 25 25448820 the memory of the microinstruction register is connected to the first input of the sixth OR element and through the third delay element to the second inputs of the first and second AND elements and the first input of the eighth AND element, the output of which is connected to the first input of the seventh OR element, the output of which is connected to the second input The first element OR and, through the fourth delay element, with the second input of the third element OR, and through the fourth delay element, with the second input of the fifth element, AND, the output of which is connected to the single input of the trigger trigger, th output control unit via the sixth delay unit - to the first input of the eighth OR gate and tri-: The 20th output of the control unit, the initial setup register of micro-commands is connected to the second input of the second OR element, to the single control trigger input, to the eleventh output of the control unit, and through the seventh delay element to the fourth input of the first OR element and the third input of the fourth OR element; the control mode of the combinational circuits of the micro-command register is connected to the third input of the second OR element and the first input of the ninth OR element, the second output of which is connected to the output of trolley bus register microinstruction, the output end of the test the search feature mode defects in the control memory elements is connected to the output of the sixteenth control block, the fifteenth yield thirty 40 which is connected to the output of the ninth element OR, the seventh, eighth and tenth outputs of the control unit are connected to the output of the sixth element OR, to the output of the eighth element OR and the output of the second element OR, respectively, while the output of the eighth element and connected to the eighth delay element the first input of the first OR element and the fourth output of the fourth OR element, the single output of the start trigger is connected to the third input of the first AND element, to the third input of the second And element and the first input of the ninth AND element, the output of which th is connected to the eighth input element vtorn 21 OR, the zero output of the trigger trigger is connected to the second input of the eighth element AND and the first input of the tenth element AND, the second input is connected to the output of the fourth element AND and the second input of the ninth element AND, the single output of the control trigger is connected to the second input of the fourth element AND , the zero output of the control trigger is connected to the second inputs of the third and seventh elements And, the output of which is connected to the second input of the sixth 448822. the OR element, the output of the first AND element is connected to the sixth and fifth inputs of the corresponding first and fourth OR elements, the output of the second AND element is connected to the second the input of the seventh SHS element, with the eighth input of the first OR element connected to the device bypass input when defects are detected, 10 output of the tenth AND element is connected to the seventh input of the first OR element and with the sixth input of the fourth OR element. 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