SU1249694A1 - Generator of step voltage - Google Patents

Abstract

The invention relates to the pulse technique and can be used in the formation of voltages with a high stability of the parameters you; A LO signal. The aim of the invention is to expand the functionality of the device by ensuring the formation of two independent signals. Into a device containing output keys 1 and 2, memorizing elements 3 and 4, adder 5, input key 6, first device input 7, clock generator 8, a second input key 9, elements OR 1O and 11, memorizing element 12 are entered to achieve the goal. , the third output 13, the second input 14 of the device and the new connections. The storage elements 3, 4 and 12 are made, respectively, on switches 15, 18 and 21, capacitors 16, 19 and 22, amplifiers 17, 20 and 23, the device ensures the formation of two independent ones. stepwise voltage by first processing one input signal, then the other, independently of the first input signal, by quantizing without transforming information. The results of processing each of the signals are output to the corresponding individual output of the device. 1 il. with S (L 70 1chE CD O CO 4i

Description

The invention relates to a pulse technique and can be used, for example, in the formation of voltages with a high stability of the parameters of the output signal.

The aim of the invention is to expand the functionality by providing the formation of two independent signals.

Figure 1 shows the structural electrical circuit of the device; 2 shows diagrams for the operation of the device.

The device contains the first and second output keys 1 and 2, the inputs of which are connected respectively to the outputs of the first and second memory. 3 and 4, and the outputs are connected to the first input of the adder 5, the second input of which is connected to the output of the first input key 6, the input of which is connected to the first input 7 of the device, and the control input to the first output of the clock generator 8 second output which is connected to the control input of the first memory element 4, the third output is connected to the control input of the second output key 2, the fourth output is connected to the control input of the second memory element 3, the second input key 9, the first and second elements OR 10 and 11, third memory element 12 and the third output key 13, the output of which is connected to the first input of the adder 5, the input to the output of the third storage element 12, the input of which is connected to the output of the adder 5, the third input of which is connected to the output of the second input key 9, the input of which is connected to the second an input 14 of the device, and a control input with a third output of the clock generator 8, the first input of the first element OR 10 whose output is connected to the control input of the third memory element 12, and the second input - with the control input of the first output key Cha 1 and the first output of the clock generator 8, the fourth output of which is connected to the first input of the second element OR 11, the output of which is connected to the control input of the third output key 13, the second input to the second output of the clock generator 8.

The storage element 3 is made on the key 15, the capacitor 16 and usi

five

0

five

0

S

0

five

0

The gate 17, the memory element h is on the key 18, the capacitor 19 and the amplifier 20, the memory element 12 is on the key 21, the capacitor 22 and the amplifier 23.

The device works as follows.

The clock generator 8 in one cycle of operation forms four pulsed voltages shifted relative to each other by 180 ° (fig. 2a, 6.6 ig)

The impulse voltage (Fig. 2l) controls the operation of the keys 6 and 1 and, through the IL 10 element, the operation of the key 21; the pulse voltage (Fig. 2c)) controls the operation of the keys 15 and, through the OR 11 element, the operation of the key 13; the pulse voltage (Fig. 2 and) controls the operation of the key 9 and 2 and, through the element OR 10, the operation of the key 21; the pulse voltage (Fig. 2d) controls the operation of the key 18 and, through the element OR 11, controls the operation of the key 13.

In the presence of positive pulses at the outputs of the clock generator, the keys are opened, and in the absence of pulses they are closed.

. The adder 5 has, on the first input, the transfer coefficient is one, on the second input - K,, and on the third input - k.

Capacitors 22, 16 and 19 before switching on the circuit are discharged.

In the first cycle of the clock generator, when the first pulse voltage arrives, the keys 6,21 and 1 open

At the output of the adder 5, a voltage KvU / is set, where and, is the voltage at the input 7 of the device, and is the transmission coefficient at the second input of the adder. In this case, the capacitor 22 is charged through the low output impedance of the adder 5 through the open key 21 to a voltage K, and,.

The circuit parameters of the storage element 12 are chosen so that the following relations hold:

Ri -R ,, - C.t,

(12)

where RI is the output impedance

adder 5;

C is the storage capacitor capacity;

is equal to K, and the second input of the adder, whose transmission coefficient is equal to one, receives the voltage from the capacitor 16, equal to K, U,

Upon receipt of the second pulse voltage, the keys 13 and 15 are opened.

I - the duration of the manager

 impulse;

Rjj is the input impedance of the matching amplifier of the memory element. 5 When inequality (1) is fulfilled, the voltage to which the capacitor of storage element 12 is charged does not depend on the change in the value of its capacitance, and when unequal input of adder 5 is performed, the voltage across the capacitor - the key 15 is rewritten to the con- stant unchanged during the time that the key of the storage element is closed.

Upon receipt of the second impulse voltage, the keys 15 and 13 are opened.

The voltage is equal to K, U, from the output of the amplifier through the key 13 enters

The voltage equal to 2-K, Ui, from the output of amplifier 23 goes to the sensor 16, and the voltage on the output terminal .24 becomes equal to 2-K, -i, (Fig. 2) ...

Thus, at the first output of the device, the voltage increases stepwise and becomes equal to 2 K, -U,,

When the third impulse voltage arrives, the keys 9 are opened at the first input of the adder 5, the coefficient is 20 21 and 2, the transfer rate of which is equal to one. As a consequence, through the public key 15, the capacitor 16 is charged to the voltage K | U., (FIG. 2 e), which is fed to the output terminal 24.

25

The output of the adder 5 sets a voltage equal to (} and the capacitor 22 is charged before the voltage, since the third input of the adder receives the voltage U and the transmission coefficient on this input is equal to Ku, and the first input of the adder, whose transmission coefficient equal to one, the voltage from the capacitor 19 comes, equal to K, U.

35

When the third pulse voltage arrives, keys 9, 21 and 2 are opened.

At the output of the adder 5, a voltage is set, where U is 30 the input voltage G4 of the device, and Xj is the transmission coefficient at the third input of the adder. In this case, the capacitor 22 is charged through the small you. adder resistance 5 to the voltage K Uj

Upon receipt of the fourth impulse voltage, the keys 18 and 13 are opened.

Voltage equal to. Kj U,, from the output of the amplifier .23 enters through the public key 13 to the first input of the adder 5, the ratio of which is equal to one. As a consequence, through the public key 18, the capacitor 19 is charged. Up to the voltage K, -U, (FIG. Ze), which is supplied to the output terminal 25.

45

In the second cycle of operation of the clock generator, when the first pulse voltage arrives, the keys 6, 21 and 1 open.

At the output of the adder, the voltage is set to 2K, and, and the capacitor 22 is charged to voltage 2 (, and, since the voltage U is applied to the second input of the adder, and the transmission coefficient on this input is

6944

is equal to K, and the second input of the adder, whose transmission coefficient is equal to one, receives the voltage from the capacitor 16, equal to K, U,

Upon receipt of the second pulse voltage, the keys 13 and 15 are opened.

5 The second input of the adder 5 and through the open key 15 is rewritten to the

the input of the adder 5 and through the open key 15 is rewritten to the

The voltage equal to 2-K, Ui, from the output of the amplifier 23 is fed to the first input of the adder 5 and through the open key 15 is copied to the constant

The capacitor 16, and the voltage at the output terminal .24 becomes equal to 2 -K, -i, (FIG. 2) ...

Thus, at the first output of the device, the voltage increases stepwise and becomes equal to 2 K, -U,,

When the third pulse voltage arrives, keys 9, 21 and 2 open,

The output of the adder 5 sets a voltage equal to (} and the capacitor 22 is charged before the voltage, since the third input of the adder receives the voltage U and the transmission coefficient on this input is equal to Ku, and the first input of the adder, whose transmission coefficient equal to one, the voltage from the capacitor 19 comes, equal to K, U.

When the fourth pulse voltage arrives, it opens. keys 18 and 13.

The voltage equal to, from the output of the amplifier 23 is fed to the first input of the adder and through the public key 18 is copied to the capacitor 19, and the voltage at the output terminal 25 becomes equal (Fig. 2e).

Thus, at the second output of the device, the voltage gradually increases and becomes equal. Further, the processes are repeated with a period of 4T.

As a result, two independent step voltages are generated at the output terminals 24 and 25, increasing linearly and

shifted by time 2, with the increment of the first step voltage being K., - U, and the increment of the second step voltage being Kj and,.

In this case, the storage element 12 is used as a temporary operating memory element for storing the sum of the signals, working for two

integrator, which allows for a separate summation of changes in two independent voltages with a clock frequency over the time interval

The device provides for the formation of two independent stepwise voltages due to the sequential processing of one input signal, then the other, independently of the first input signal, by quantizing without converting information, and as a result of processing, each of the signals is output to the corresponding separate device code. This saves equipment by using one key and one memory element for both integrators.

In addition, the generated step voltages are characterized by high stability, since its parameters are determined by the total instability of the transfer coefficients of the adder and the matching amplifiers of the storage elements. When using high-frequency resistors in the step voltage shaper circuit, the total instability of the transfer coefficients is easily achievable by the end of the storage period, not exceeding 1%.

Claims (1)

At the same time, the temporary instability of the circuit parameters, caused by the temporal instability and capacitance capacitance value, is eliminated, which allows, more than an order of magnitude, to increase the temporal stability of the parameters of the output signal of the transformer and the consumer and ensure the formation of two independent step voltages accrued by a linear law. Invention Formula A step voltage shaper containing the first and second output keys, the inputs of which are connected respectively to the outputs of the first and second storage elements, and the outputs are connected to the first input of the adder, the second input of which is connected to the output of the first input key the device input, and the control input - with the first output of the clock generator, the second output of which is connected to the control input of the first storage element, the third output - with the control input of the second output c On the other hand, a fourth output with a control input of the second storage element, characterized in that, in order to extend the functionality by providing a form of matching two independent output signals, a second input key, first and second SHS elements, a third storage element and the third output key, the output of which is connected to the first input of the adder, the input is connected to the output of the third storage element, the input of which is connected to the output of the adder, the third input of which is connected to the output of the second output key, od which is connected to the second input of the device, and the control input - to the third output of the clock generator, the first input of the first OR element, the output of which is connected to the control input of the third storage element, and the second input with the control input of the first output key and the first output of the clock generator, the fourth output of which is connected to the first input of the second SHS element, the output of which is connected to the control input of the third output key, the second input with the second output of the clock generator. FIG. g Editor N. Margolin Compiled by A.Gorbachev Tehred L.Oleinik Order 4338/58 Circulation 816 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4 Proofreader S. Cherni