SU1247892A1 - Matrix calculating device - Google Patents

Abstract

The invention relates to computing and can be used in high-speed processors and specialized computing devices. The purpose of the invention is to improve speed. The device calculates the sinX and COSX functions using the digit-by-digit method. The device contains submatrix 1, which contains two rows of computational cells, and submatrix 3, which contains one row each, as well as multiplexer 2. Each computational cell contains a modulo 2 adder and a one-bit adder. In addition, submatrices 1 and 3 contain the elements HE.1.s.p.f-ly, 5 Il. i (L 1 5: .u n t: rig.}

Description

 12

The invention relates to computing and can be used in high-speed processors and specialized computing devices.

The aim of the invention is to improve speed.

FIG. 1 shows a block diagram of the proposed device; FIG. 2 shows a part of the matrix containing in each row two rows of computational cells; in fig. 3 - part of the matrix, containing p each row of one row of cells; in fig. 4 is a block diagram of a computational cell; in fig. 5 is a block diagram of two viral cells.

The device contains a part of matrix 1 with two rows of computational cells in a row, multiplexer 2, part of matrix 3 with one row of computational cells in a row, inputs 4-6 of the first part of the matrix, inputs 7 and 8 of the multiplexer, input 9 of the device , outputs 10 and 11 of the multiplexer, output 12 of the device, and the matrix contains computational cells 13 and the elements. NOT 14. °

Each computational cell 13 contains an adder 15 modulo two, a one-digit adder 16, inputs 17-20 and outputs 21-23.

The truth table of computational cell 13 is shown below.

The matrix computing device calculates the sin S and COSV elementary functions using the digit-zag-digit method.

The recursive relations describing the digit-by-digit algorithm for the sin и and the cozy functions are as follows:

Table continuation

about 1 1 about about 1 1 about about 1 1

1 about 1

about 1 about 1

about 1 about 1

about about 1 1 1 1 1 1 1 1

eleven

1 о 1 1 1 о о о о

about o 1 1

about about 1

about 1 1 1

1.4, 0; -.arctg2- Stage I 1. signQ;

II

) .41

,

 -, -. y,

 W; , 2-,

dd where X., y. - current coordinates of the vector torus; x, y - final coordinates

vectors;

n is the number of iteration steps. j Initial conditions: о, Хд 1 / kv УО О, where k is the deformation coefficient of the vector, depending only on the basis of iterations:

50

n J (1 +)

l-o

Results of calculations: at sinU; x cosV. .

The calculation of the whale matrix performs 55 the second stage of the algorithm and works as follows.

Initial conditions are supplied to the inputs 4 of the matrix, and inputs 5 to the matrix 3

Reeds are the initial conditions, the inputs 6 are the values of the control signals. +1 is coded with zero and -1 is coded with one. Each line of computational cells 13 of the computational submatrix 1 performs two operations of algebraic summation. At outputs 23 of the second row of computational cells of the 13 .i-th line of submatrix 1, we have the value of y. , and at outputs 23 of the first p of yes computational cells 13, we have the value x-. Wherein

P ; Yeah.

UE Ur p

P-

e-11,.

x, 2

Since the values of sin4 and cozy are usually not required at the same time, it is possible to control the calculation of the sine or cosine using the control signal f.

S D f ZI.

. G2

where f (+1; -1}, with +1 being encoded as zero, and -1 being encoded as one,

x if f 1 if f 0;

D pt b ,.

“(U :: .. {

if f o if f 1,

sinV if f 0. cos f, if f 1,

Thus, the matrix can be constructed from submatrix 1, which calculates the value of x g and y; from multiplexer 2 whose operation is described by

(Xp if f oh

/ c 1.

yj, if f 1;

X, if f 1, y, if f Oh,

from submatrix 3, calculating si

fsin4, if f О, tcosM, if f 1.

Formula inventions

1. Matrix computing device containing a group of elements

Claims (2)

one - about s at 2478924 NOT and the matrix of computational cells, the matrix from the first to the 1st row (where f is the largest integer from half the last column number is 5 tons, where m is the device size), contains two rows of computational ECs, each row with t + 1 according to claim (where n is the number of iterations) contains one group of computational cells, with 10 input setting the mode of computational cells in the i-th row (i 1, 2, ..., p) and the JM column (J 1, 2, .. ., t) is connected to the output of the task setting of the computational cell of the same row (j G5 1) -th column, the input of the task of the mode of the computational cell of the second row ne The first to tth row of the first column is connected through the corresponding element NOT of the group with the task input 20 modes of computational cell addition the same column, the same row of the first row and the device mode setting input, the transfer input of each computational cell in the i-th row and the JM column 25 are connected respectively to the transfer output of the computational cell of the same row and the same row (j + 1) th column, the transfer input of each computational cell of the tth column is connected to the output of the mode of the same computational cell, the inputs of the first term of the computational cells from the second to the tth lines in the JM capital are connected to the sum of the computational cells (i - 1 ) -th line (j - i + 1) - The second column of the other row is yes, the input of the second term of each computational cell of the i-th row except (t + 1) -th j-ro column is connected respectively with the output of the sum of the computational cell of the same row, of the same column (i - 1 ) -th row, the input of the second term of each computational cell of the first row of the first row is connected respectively to the input of the first term of the computational cell of the second row of the same column, the same row and connected to the first group of information inputs of the device, the input of the second term of each doi computational cell with wto; The rag of the first row is combined with the input of the term of the computational cell of the first row of the same column, the same line and connected to the second information input of the device, the output of the sum of the i-th (i. 1, ..., t - 1) computational cell with per35 40 45 50 the first (f - 1) -th row of the first column is connected to the input of the first term of the computational cells from the second to (i + 1) -th columns (i + + 1) -th row of another row, the output of the sum of each v1 column number of the last row connected to the output of the device, characterized by the fact that, in order to develop a fast action, a multiplexer and a group of modulo-two adders are introduced into it, the control input of the multiplexer is connected to the input of the device function selection, the outputs of the sum of the first and second computation cells The rows of the tth row are connected respectively. the first and second information inputs of the multiplexer, the first output of which is connected to the input of the first term (Е + + 1) -th row, the second output of the multiplexer is connected to the input of the second term of the computational cell (t + 1) -th row, The computational cell in (tq) row (q 1, 2, ..., p - I) of the first column is connected to the output of the corresponding modulo-two adder, the first and second inputs of which are connected respectively to the device mode input and the group of device control inputs , entrance the first term of the computational cell (t + 1) -th row of the first column is connected to the input of the first term of the computational cell (f + q) -th row and from the first to (f + q) -and columns, the input of the first term of the computational cell (+ + 1) -th row (f + k) -ro of the column (k 2, 3,, .., ha - J) is connected to the input of the first term of the computational cell (t + q) -th row (t + f- q - k t .1) -th column. 2. A pop, 1 device, characterized in that each computational cell contains a modulo two adder and a one-digit adder, the first and second bit inputs of which are connected respectively to the modulator two output and the second addend of the second cell, the mode setting input connected to the first input of a torus modulo two and the output of setting the cell mode, the transfer input of which is connected to the transfer input of a one-bit adder, the output of the sum and transfer of which is connected to the corresponding output of the cell, the input of the first lagged which is connected to the second input of the modulo two adder. "|| 5 11-5 "IiS G.1. (pue, J 17 21 13 / A IB 13 22 IS one 20 23 FIG. V 23 figure 5  2 Editor I.Rybchenko Compiled by A.Zorin Tehredn.Hodanich Proofreader A.Obruchar Order 4128/50 Circulation 671 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4  23