SU1242966A1 - Device for checking program execution time - Google Patents

Abstract

The invention relates to computing and can be used in computing systems consisting of high-performance computers controlled by autonomous operating systems. The aim of the invention is to increase the reliability of control of the computing system. In a computer system consisting of a computer with autonomous operating systems, during the exchange of messages, malfunctions are possible both in the computers themselves and in the channels connecting them. A system with start-stop transmission of information as a result of a failure may be in the so-called hangup state, when the propagation of information through any device stops. In this case, network subscribers do not receive any information about the reason for termination of exchanges and continue to send messages to the system, filling all the buffers in the switching system. The connection between the devices by means of the equipment serving the control bus is not broken, and this allows one of the subscribers to become a system manager. The proposed devices, which are part of each subscriber of the system and interconnected by means of the dispatcher bus, can initiate system normalization. As a result of the normalization, the part of the equipment in the system where the failure occurred is differentially zeroed. After zeroing, only one task is stopped, which can be regenerated with the help of an autonomous operating system. Rest. tasks continue to be solved without restarting after completion of system normalization. The goal is achieved by the fact that three AND elements, one element 2И-OR, one element ЗИ-OR, a priority block, two threshold elements, two delay elements are entered into the device. 1 il. from to GcheE 4 ts O5 G5

Description

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1242966

The invention relates to computing,

technology and can be used in computing systems consisting of high-performance computers controlled by autonomous operating systems.

The aim of the invention is to increase the reliability of controlling the computing system by introducing additional means to normalize the state of subscribers.

The drawing shows a diagram of the device.

The device contains the first delay element 1, the start trigger 2, the temporary control, the first element 3, the ready trigger 4, the generator 5 time stamps, the zero zero trigger 6, the first 3 element ZI-OR 7, the second element 3 ZIII-SH 8, the fourth element I 9, the third element ZI-UTI 10, the priority block 11, the threshold element 12. high level, the threshold element 13 low level, element 2I-OR 14, the third element And 15, the second element And 16, the second element 17 of the snaps, the third element 18 delays. This device is located in each system’s oblique. The devices are connected with one bus of the PShA dispatcher, as well as with a common zeroing bus of the EIS system.

The device works in the following way.

In the normal course of program execution, generator 5, via delay element 1, periodically blinks trigger 2 signals, and from trigger 4 output, there are signals of pairing ready for issuing messages, the normal state of which is single. When sending a message to the channel of a message, the message readiness signal (trigger 4) is reset on bus A to the zero state by sending a message to the channel, and trigger 4 sends a signal on the message B sent on the channel to the channel B. In the case of a subscriber readiness zero state, trigger 2 is set to a unit with a timestamp and waits for the next timestamp. Since the interval between the tags is significantly longer than the response time in the switching network, during normal operation, the ready signal has time to be established on the bus B into a single state until the next time.

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tag and trigger 2 is reset to zero through element 3. If the mate readiness signal on trigger 4 continues to remain in the zero state when the new time stamp arrives, it is considered that the response to the sent message did not come as a result of a failure in the switching network or in the subscriber adapter, KOTopoNfy sent a message. In the case of a single state of trigger 2, a new time stamp sets the Vx state of one trigger 6 to zero. When the signal T 6 appears, the voltage on the SchD dispatcher's bus starts to increase linearly. The signal T 6 is fed to the input of the priority unit 11, which controls the amplitude of the signal on the bus 11SH in such a way that it increases with increasing current

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amplitudes; and signal, Tm, e. positive current feedback is implemented in the circuit

Before normalizing the system, it is necessary to seize the controller bus to suspend generation and transmissions; posts by. channel. Since the system can simultaneously have multiple subscriber requirements

Q on normalization, possible conflict situation, which is resolved at the level of the dispatcher's bus capture.

The formation of a normalization signal (BEC) on the third element And 15 is permitted only by the device that captures the control bus. Thus, when multiple requirements appear, normalization is performed with only one device, and the remaining requirements are cleared as a result of normalization.

The nullification bus (BDL) is organized according to the principle of direct integration of all sources and receivers of the nullification signal of each subscriber of the system. Therefore, the subscriber entering the zeroing signals perceives them on a par with the other subscribers. The device can operate in the mode of issuing normalization signals to the WO bus when the subscriber in the system is the initiator of normalization and in the mode of receiving normalization signals when the subscriber is not the initiator.

If the subscriber of the system is the initiator of the normalization, the signal T 6 sets in one state the element ZI-OR 7 and T 7 (BGS), When

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the coincidence of the single state of the T 6 signal and the signal from the priority block 11 (ASCH) is set in the single state the second element ZI-OR 8 (BPS), element 2I-OR 14 and the third element AND 15.

If the subscriber of the system is not the initiator of the normalization, the BGS and BTS signals are set as follows.

The threshold element 13 (GPNTSN) is activated from a low voltage level on the TsCH bus; Signal HSSSCH when coinciding with the inverse value of signal ZSCHTS sets to one the first element ZI-IPI 7 (BGS 1), the other installation input of this element does not work, because the signals of T b and ZPS were not installed in the device of this subscriber. The threshold element 12 (HSCW) is triggered by a high voltage level on the SCH-bus. The PShchSV signal and the inverse value of the emergency call center signal arrive at the fourth element AND 9 (memory) of the subscriber capture and, if it coincides, the second element ZI-OR 8 (BPS 1) is then set to the one state. Further, such a subscriber waits for the signal to zero out on the bus 111УО, receives it to the preliminary zeroing driver 14, and an analysis of the need for normalization in the given subscriber is performed on the element 16,

In the subscriber's initializer of normalization, after setting the zeroing requirement on T 6 into a trigger unit, the BGS mode occurs, which blocks the operation of trigger 2 by locking the AND 3 element with a negative signal from the ZI-OR element 7. A setting is made between the BGS and BPS signals during which There is a refinement of the messages in the switching network and, at the time of the occurrence of the bus seizure signal, the EASC manager is set to BTS mode, when message transfer is already stopped.

The third element, And 15, when the signals of T 6 and TSCHC coincide, sends a normalization signal to the busbar switch.

Element 2I - OR 14 triggers from the coincidence of the signals coming from the priority block 11 (ASC) and the zero reset requirement trigger 6 (T 6).

Element I 16 operates at the coincidence of the signal coming from element 2I-INR 14 and the signal from unit 10

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Who is the trigger output 4. The signal WLL from the element And 16, sets the trigger 4 to one, sets the trigger 6 to zero through the second delay element 17.

The duration of the LLL signal is determined by the duration T 6, which is defined by trigger 6.

When the signal T 6 is reset to zero, the voltage on the SCHC bus starts to fall linearly. Threshold element 12 is reset to zero, the ASCR signal from priority block 11, which prohibits the operation of element 2I-OR 14, is reset to zero. IC is terminated.

Due to the uneven termination of the VLM signal in order to normalize different subscribers of the system, the unit state of the BPS signal on the ZI-YPI element 8 does not temporarily change when the T 6 signal is reset. The NGS signal maintained by the positive signal remains in the single state from the delay element 18. After the delay time after resetting the CBD signal, the BPS and BGS signals are successively reset.

The element ZI-OR 10 expresses the signal of the end of control of the KBPS device with the coincidence of high levels of the BGS signal and the inverse signal of the BPS.

The signals on buses C and D, respectively, BGS and BPS, are simultaneously the first and second outputs of the device and block the generation and transmission of subscriber messages in ka. cash during subscriber normalization.

The signal of the device control end from the bus K and the signal zeroing of the device from the bus E, which is simultaneously a sign of the end of the program, serve as outputs of the device and start the external fault buffering circuit. This scheme writes into the buffer memory the signs of resetting the EID, so that after normalization the processor, which suffered as a result of the failure, can resume the operation of the program.

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Thus, monitoring the time of executing programs and activating a program affected by a crash followed by system normalization using software and hardware increases the accuracy of the control of the computing system.

Claims (1)

Invention Formula A device for monitoring program execution time, containing the first delay element, time stamp generator, first AND element, ready trigger, zero reset trigger, time control start trigger, first and second ZI-OR elements, and the time stamp generator output is connected to the trigger input Requirements of zeroing and through the first element of the back delay - with the clock input of the start trigger of the MerfHoro control, the control start input of the device is connected to the single readiness trigger input, the inverse output of which It is connected to the first input of the first element I and the information input of the start of the time control trigger, the input of the control end of the device is connected to the zero input of the ready trigger, the output of the first element I is connected to the zero input of the start of the time control, the first output of which is connected to the information zero trigger request input The direct output of the Zero Requirement Trigger is connected to the first inputs of the first and second ZI-OR elements, characterized in that, in order to increase the reliability of the control, it has the second, third and fourth elements AND, the second and third delay elements, the third ZI-OR element, the 2I-OR element, the priority block, the high-level threshold element and the low-level threshold element, the inverse output of the ready trigger is connected to the first input of the second element And, the direct output of which is connected to the information input of the ready trigger, and through the second delay element to the second input of the second ZIL element, and is the output of the sign of the end of the device’s program execution, the direct output is the trigger tre0 five 0 five 0 five 0 five The zero reset is connected to the first input of the third element AND, the first input of the priority block and the first input of the element 2И-OR, the output of which is connected to the second input of the second element AND, the inverse output of the zero reset trigger is connected to the first input of the third element ZI-1ShI, whose output is The output of the control end of the device, the forward output of the first element is connected to the second input of the third element ZI-OR, and is the first output of the device, the inverse output of the first element ZI-OR is connected to the second input of the first And, the information input of the device is connected to the second input of the priority block and to the inputs of the threshold elements of the low and high levels, the direct output of the priority block is connected to the second input of the 2I-OR element, the third input of the second ZI-1SHI element and the second input of the third AND element, the output of which is connected to the third input of element 2I-OR and is the output of zeroing the device, the inverse output of the priority block is connected to the second input of the first element ZILOR, to the first input of the fourth element AND, the output of which is connected to the fourth input and the fourth input of the second element ZI-OR, the inverse output of which is connected to the third input of the third element ZI-STI, direct; the second element ZI-OR is connected to the third input of the first element ZI-RSHI and is the second output of the device , the output of the high-level threshold element is connected to the second input of the fourth element AND, the output of the low-level threshold element is connected to the fourth inputs of the first and third elements ZI-OR, the inverse output of the second element AND through the third delay element en with zero input trigger zero reset.