SU1242941A1 - Stochastic integrator - Google Patents

Abstract

The invention relates to the field of measurement, monitoring and control, and can find application in all areas of science and technology where it is required to make measurement of signals by the method of statistical tests. The purpose of the invention is to increase the measurement accuracy. The goal is achieved by including into the device blocks that adapt the generation range of an auxiliary uniformly distributed signal according to the degree of deviation from the middle of the range. The novelty of the proposed probabilistic integrator lies in the fact that it includes the second averaging block and the arytic block, which specifies the optimum width of the latter by the deviation of the signal from the middle of the range. In addition, to accomplish the task, functional implementation of the arithmetic unit and the scaling unit are characteristic. F-ly, 3 W1. F (L to 4; 1C with 4i

Description

The invention relates to the field of measurement, control and management, and can be used in information-measuring technology, radio engineering and instrument making.

The purpose of the invention is to increase the measurement accuracy.

Figure 1 shows the structural scheme of a probabilistic integrator; figure 2 - scheme of the arithmetic unit; FIG. 3 is a scaling block diagram.

The probability integrator (Fig. 1) comprises a comparison circuit 1, averaging unit 2 j scaling unit 3, averaging unit 4, multiplying unit 5 arithmetic unit 6, noise generator 7 and measuring range storage unit 8.

The arithmetic unit 6 (FIG. 2) contains the first 9 and second 10 registers the assignment of constants, the adder 11, the multiplier 12, and the module I3 of the allocation module.

Scaling unit 3 (Fig. 3) contains registers 14 and 15 of specifying constants, divider 16, adder 17 and multiplier 18.

 The integrator corrects the ⦥ in accordance with the expected variation in signal values, and in such a way as to minimize the loss in integration accuracy.

The principle of correction g is based on the following. The first component of the integration error is the sampling error. Since the sampling error is proportional to the width of the & , then to reduce this component, it is necessary to decrease the range of d. However, if the measured signal is shifted relative to the middle of the range d, this causes a shift in the evaluation of its integral value, and the shift value is greater, than 4, therefore taking into account both factors for a given deviation IS I, set the best (in terms of measurement error) optimal value of l

OPG

band width l.

Empirical relationship between the optimal width Ajjf. and the deviation of ISf obtained experimentally

(results are shown in Fig. 2) and are described by a regression formula:

l 3.33 + 2.08 ISI.

If we assume that the auxiliary signal has a range of variation

- i.e. centered then

the mean value of the measured signal S coincides with the deviation relative to the middle of the range O, i.e.

S () A - l / 2 (i; / f, - - 0.5) l,

where fp is the time taken for the auxiliary signal to be measured; t is the measurement time. Since the proposed device d varies, it uses two averaging blocks. In the first averaging block, with a constant time t, which is small in comparison with the adaptation rate 4, the current estimate of the average value of the signal is carried out

one

S, ---- i dt W o

relative to some short interval f.

In the second averaging block, the estimate of S obtained at the output of the first averaging block is averaged over the entire integration interval i

- - - S

  1 J t

dt.

40 The integrator works in the following way.

45

50

One of the inputs of the comparison circuit 1, which is the input of the device, receives the measured signal 2, the other input of which receives the voltage from the output of the multiplication unit 5, evenly distributed in the range l 1

zone

l l 1

 about which

set from the output of block B. The output value of block 5 j is equal to

U.

55 where and is the optimal value of the range; Q. - evenly distributed

random value in range

3

j

 2

J.

arriving at the corresponding input of the multiplier 5 from the output of the noise generator 7.

The comparison scheme I performs the following logical operation.

but

where X. is a two-level logical cifr-nap from the output of comparison circuit 1, receiving a logical level of 1 and 0, respectively.

The 5C logic signal from the output of the comparison circuit 1 is fed to the input of averaging unit 2, which operates according to the averaging link principle with a time constant i

,

C

you

 -i- t

r t 1

And dt.

The time L determines the length of the moving interval of the averaging of the measured signal, provided that 4 remains practically unchanged in this interval. The value from the output of the averaging unit 2 is fed to the input of the mass stabilization unit 3, in which the averaged time interval i is scaled according to &

Signal3 value (

6Hv, - where.

/and.

Oh, 5) a

3 g

The maximum value of voltage that may be at the output of averaging unit 2.

The voltage from the output of scaling unit 3 is fed to the input of averaging unit 4, where the value of the signal obtained for the optimization of g is averaged with the values accumulated at previous time instants. .

-, -V1

. ".,

where is the averaging time equal to the total device operation time. The voltage from the output of block 4 average

Nini comes to the input of arithmeti242941 .4

block 6, the voltage from the output of which is equal to

and “s., 3.33 2.08 IU ,, J 3.33 + 2.08 tSt.

The output voltage of the node node is equal to

 I s i.

ten

15

25

thirty

willows., IU ,, J

20

The first register 9 stores a value equal to a constant factor of 2.08. The output voltage of the multiplier I2 is equal to

.ии ,, V ,, .2.08 2.08 (SI.

The second register 10 stores a constant value of one of the terms, equal to 3.33; The output value of the adder 11 is equal to

".., oy., / 3,33 3,334-2,08 ISL

The output voltage of the arithmetic unit 6 is equal to the optimized value of the range of the auxiliary random uniformly distributed process, is fed to the input of the storage unit 8 and is later used to measure the input signal.

At the time the integrator is switched on in the storage unit 8 for the measurement range, the initial value (possibly the maximum) is entered. Thanks to the feedback between the signals. The 35 value of the latter adapts to the value of the measured signal.

Formulas

the invention

Claims (2)

1. A probability integrator containing a comparison circuit, the first input of which is the integrator input, a second input connected to the output of the multiplication unit, the first input of which is connected to the output of the noise generator, and the output of the comparison circuit through the first averaging unit the input of the scaling unit, the second information input which is combined with the second input of the multiplication unit and connected to the output of the storage unit of the measuring range, the input of setting the initial value of the range of which is set integrator input, characterized in that, in order to improve accuracy, it contains a second averaging unit, whose input is connected to the output of the scaling unit, and the output is the output of the integrator, an arithmetic unit consisting of the first and second registers of the constants, the adder, the multiplier and the allocation node of the module whose input is connected to the output of the second averaging unit, and the output is connected to the first the input of the multiplier, the second input of which is connected to the output of the first register of setting constants, and the output of the multiplier is connected to the first input of the adder, the second input of which is connected to the output of the second register of setting constants, and the output of the adder It is connected to the information input of the measuring range storage unit. FIG. 2 2. The integrator of claim 1, which is based on the fact that the scaling block contains the first and second registers of the constants, the adder, multiplier and divider, the first input of which is the first information input of the block, the second input is connected to the output of the first register, and the output of the divider is connected to the first input of the adder, the second input of which is connected to the output of the second register, and the output of the adder is connected to the first input of the multiplier, 15 the second input and output of which are respectively the second input and output of the block. ten