SU1238247A1 - Adaptive corrector of intersymbol signal distortions - Google Patents

Abstract

This invention relates to electro-cjBH3H. Correction accuracy is improved. The device contains a harmonic equalizer 1, consisting of an analog, multi-drop line 2, delay, attenuator 4 regulators and adder 5, a decisive unit (PE) 6, a subtraction unit 7, a multiplier 8, units 9 for calculating weight coefficients and an optimizer of adaytaschi coefficients (OKA ) 10, consisting of two shift registers 11 and 12, comparison unit 13, two (L co 00 4ib

Description

RB 14 and 15 and a reversible counter (PC) 16. In OKA 10, using registers II and 12 of shear, comparator block 13 and RB14, the magnitude of the correction error is estimated and makes a decision to reduce or increase per unit adaptation coefficient. The magnitude of the adaptation coefficient is determined by the contents of PC 16. The mode of operation of PC 16 is determined by RB 15 according to the magnitude of the correction error. If this value exceeds the predetermined threshold, then

The invention relates to telecommunications and can be used in data transmission systems for correcting intersymbol distortions of a signal in receiving devices, including fiber-optic communication lines.

The purpose of the invention is to improve the accuracy of the correction.

The drawing shows a structural electrical circuit of the adaptive corrector of intersymbol distortion of the signal.

The adaptive intersymbol distortion corrector (AKMSI) of the signal contains a harmonic equalizer 1 consisting of an analog multi-tap delay line 2 including delay elements 3, damping regulators 4 and adder 5, decisive block 6 subtraction unit 7, multiplier 8, calculation blocks 9 weighting factors, optimizer 10 adaptation factors. The optimizer 10 of the adaptation coefficients contains the first 11 and second 12 shift registers, a comparison block 13, the first 14 and second 15 decision blocks, and a reversible counter 16.

AKMSI signal works as follows.

To the input of the analog multi-branch line 2 delays, a video signal is fed. Each of the 3 delay delay elements delays this signal by an amount equal to the clock interval. Branches analog multi-line 2 for 38247

The output of the PC 16 is kept at the maximum combination. the device operates with a maximum adaptation coefficient before exiting the specified zone. After this, the adaptation coefficient change begins. With a sudden change in the channel state, the RB 1.5 automatically blocks the operation of the PC 16 and at its output sets the maximum combination, i.e. the adaptation coefficient becomes maximum. The goal is achieved by introducing OKA 10. 1 Il.

holders through damping regulators 4, which are digital potentiometers, are connected to adder 5, the output of which is the output of harmonic equalizer 1. The corrected signal from the output of adder 5 is fed to the input of decisive unit 6, the output of which. is the output of the harmonic equalizer 1. The output of decision block 6 is also connected to the input of block 7-deduction, in which the formation of an error signal is realized. (), obtained as the difference of the signal from the output of the adder 5

and the signal from the output of decisive block 6, i.e. estimates of the corrected signal. The error signals from the output of the subtraction unit 7 are fed to the input of the multiplier 8, where it is carried out

multiplication by the adaptation coefficient of M.Valichin of this coefficient is measured during the operation of the AKMSI signal as follows.

At the beginning of the j-ro correction stage, the error value is recorded in the shift register 11, after which the weights are adjusted in the taps of the analog multi-drop delay line 2. At the beginning of the (j + l) -ro correction step, the error signal (j) is rewritten from the first shift register 11 to the second shift register 12, and the newly obtained value is written to the first shift register 11

errors (errors) after what the pr9- compares them in block 13

comparison, the signal at the output of which is proportional to the change in the error at the J – M correction stage. This signal is fed to the input of the first decision block 14 of the optimizer 10, where its value is estimated and the decision is made to reduce or increase by one the adaptation coefficient. The content of the reversible counter Iff, which determines the value of the adaptation coefficient, in this case is changed by one. The second decision block 15 of the optimizer 10 determines the mode of operation of the reversing counter 16 by the magnitude of the error –correction (error). If the error value exceeds a certain predetermined threshold, then the maximum combination is maintained at the output of the reversing counter 16, and the corrector works maximum adaptation coefficient before leaving the specified zone. After this, the change begins.

adaptation factor as described above. With a sudden change in the channel state, the second decision block 15 of the miser 10 automatically blocks the operation of the reversing counter 16, on. the output of which establishes the maximum combination, i.e. adaptation coefficient becomes maximum

Claims (1)

Invention Formula An adaptive intersymbol distortion corrector containing a harmonic corrector consisting of an analog multi-drop delay line, decay controllers, and an adder decisive block, a subtraction block, a multiplier, and n blocks for calculating weighting coefficients, with input, output, and each analog tap. multi-lead delay lines are connected to the first input of the corresponding regulator Editor Y. Petrushko Compiled by Sh. Evn n Tehred M. Khodanych Order 3305/58 Circulation 624 Subscription VNRSHPI State Committee of the USSR for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, ul. Project, 4  attenuator, the output of each of which is connected to the corresponding input of the adder, the output of which is connected to the input of the decision block and the first input of the subtractor, the second input of which is connected to the decoding block code, and the output to the first input of the multiplier, whose output is connected to the combined the first inputs of the weight calculation blocks; the second input of the first and last weight calculation blocks is connected to the input and output of the analog multiturn delay line, the second input of each of the pp -2 weighting factors calculation blocks is connected to the corresponding taps of the analog multipath delay, and the output of each of the g blocks of the weighting factors calculation is connected to the second input of the corresponding attenuation controller, which differs in order to improve the accuracy of the correction, the adaptation coefficients optimizer, consisting of the first, second shift registers and the comparison unit, connected in series, is inserted into it; the input of which is connected to the output of the first shift register, the first and second decision blocks and the reversible counter; the combined inputs of the first shift register and the second decision block of the adaptation coefficient optimizer are connected to the output of the subtractor, the output of the match block is connected to the input of the first decision block, the output of which connected to the first input of the reversible counter, the second input of which is connected to the output of the second decision block, and the output of the reversible counter is connected to the second input of the multiplier. Proofreader V. But ha