SU1236599A1 - Generator of pulse delay - Google Patents

Abstract

The invention relates to a pulse technique and can be used in automation and computing devices for delaying pulses without saving them || . initial durability. The purpose of the invention, the extension of the field of application, is achieved by increasing the range of generated delays. To do this, five resistors 5, 7, 8, 9, and 10 and a comparator 11 with inverting 1-6 and non-inverting 17 inputs are entered into the driver. In addition, the driver contains a trigger 1 with a single 14 and zero 15 output i, diodes 2 and 3, a capacitor 4, a resistor 6, the bus - input 12 and output 13. An op amp with differential inputs is used as a comparator. 2 Il. S / J o with O5 SP with co f1 / g.

Description

The invention relates to an impulse technique and is intended for use in automation and computing devices for delaying pulses without preserving their original duration.

The purpose of the invention is to expand the field of application by increasing the range of generated delays.

FIG. 1 shows a device diagram; in fig. 2 shows time diagrams of voltages at the corresponding points of the circuit1, explaining the operation of the device.

The device contains BV-trigger 1 diodes 2 and 3, capacitor 4, resistors 5–10, comparator 11, input bus 12, output bus 13. Additionally, the diagram shows single output 14 of the trigger, zero output 15 of the trigger, inverting input 16 comparator, non-inverting input 17 of the comparator. 5, for example, an operational amplifier with differential inputs, is used as a comparator.

The single and zero outputs of RS-trgera 1, respectively, through diodes 2 and 3 are connected to the terminals of the capacitor 4.5, which are connected through resistors 6 and 7 to the power source 18 and through resistors 9 and 10 to riHBepTKp; i-o4eMy and non-inverter, and to it the inputs of comparator 11, connected respectively through resistors 8 and 5 with zero and single codes of nS-flip-flop I; the unit input of which is the input 12 of the device, and the zero input is connected to the output of the combinator 11 and is the output 1 of the device. Capacitor 4 is connected to the anodes of diodes 2 and 3, which allows to exclude a change in the level of the logical unit at the outputs of the trigger when recharging, dah capacitor,

The pulse delay driver operates as follows.

In the initial state, on the input driver 12, the output bus 13 and the zero code of the trigger 1 is a level of the locking unit 1y. At the single output of trigger 1, the logic level is zero. Capacitor 4 is charged with current flowing at the source 18 of power supply resistor 7 - capacitor 4 - diode 2 open our single output of trigger 1, Inverting 16 and non-inactive

rotating the 17 inputs of the comparator I1 voltage with, responsibly equal

-" -.R. 52. tt

16 R8 + R9 17 R5

RI + RIO + RS

where E is the power source voltage.

At the same time, and, -,

and. These levels

voltages are threshold and in the time diagrams of FIG. 2 they are designated respectively 1 p „p.1 and U ,, op.

FIG. 2 timing diagrams are presented for the case of a symmetric scheme of the device, i.e. when R6 R7, R9 R10, R5 R8.

When a triggering pulse arrives, trigger 1 is switched, and state 1 is set at a single output, and at zero O. This results in that the connector -1cator 4 is connected by a plate, charged by potential plus, to the Earth bus (via diode 3 and open our zero trigger output), and the plate charged with potential minus through resistor 6 to power supply 1B and through resistor 9 to inverter input of comparator 11. Thus, a single state is maintained at the output of the comparator until Nala at the inverting input becomes greater than the signal level at the noninverting input. If the comparator output had not been connected to the zero input of the trigger, then the inverter would be:) The input 16 of the comparator 11 would set a voltage

and E is Si2-.

16 R5 + RIO

and the non-inverting input would be

17 remains -t

 E

 Z5 + R10

where

eleven.

sixteen

However, since the output of comparator 11 is connected to the zero input of the trigger, then: only the voltage U at the inverting input exceeds the voltage U, at the non-inverting input, the output state of the comparator 11 is set to O, which switches the trigger 1 to the initial state i.e. On the single output, the state O is set to zero. This leads to the fact that the capacitor 4 is

3

connected by the plate, charged by the potential plus, to the common earth bus {through diode 2 and open single output of the trigger), and the plate charged by the potential minus, through the resistor 7 to the power source 18 and through the resistor 10 to the non-inverting input of the comparator 11 Thereby, state O is maintained at the output of the comparator until the signal level at the non-inverting input exceeds the voltage level at the inverting input of the comparator, after which state 1 is set at the output of the comparator.

Thus, over time. devices on the output bus i 3 a pulse is formed that is delayed relative to the input one. The delay time is determined by the duration of the first recharge of capacitor A, and the duration of the pulse is determined by the duration of the second recharge of capacitor 4.

It can be considered that the device has zero recovery time, since the values of the Unopi ENT thresholds can be taken sufficiently close to each other, for example, differing by hundredths of a volt.

Due to the fact that the capacitor 4 is not directly connected to the outputs of the trigger, its capacity can be quite large. Resistor values (resistors pe2365994

resistors) R6 and R7, which are decisive for the constant times of the first and second processes of recharging capacitor 4, are limited to their minimum values, which are determined by the permissible currents that can flow through the open trigger output.

Claims (1)

Invention Formula A pulse delay shaper containing a BS flip-flop, a single input of which is a device input, two diodes, a resistor and a capacitor connected to the resistor and the anode of the first diode by one end, characterized in that, in order to increase the range of delays formed, five resistors and a comparator are introduced, the output of which is the output of the device and is connected to the zero input of the NE-flip-flop, the single and zero outputs to  secondly connected respectively to the cathodes of the first and second diodes and, respectively, through the second and third resistors with non-sinking and inverting inputs of the comparator connected via the fourth and fifth resistors respectively to the corresponding capacitor terminals, the anode of the second diode connected to another capacitor terminal and through a sixth resistor with a power supply width and a second output of the first resistor. sixteen Unop.1 tr por.g . FIG. 2 Editor E. Papp Compiled by A. Titov Tehred I.Popovich Order 3098/58 Circulation 816 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4 (Jnop. 2 Proofreading Kolb