SU1234991A1 - Device for converting signals - Google Patents

Abstract

The invention relates to telecommunications and m. used in digital channel formation equipment. Improves noise immunity of data transmission. The device contains a generator, as well as on the transmitting side: a switch, a scrambler, two encoders, two signal shaping units, two modulators, three adders, a DAC, an output matching unit and a decoder, and on the receiving side: an input matching unit, an amplifier with AGC, two demodulators, Hilbert converter, two ADCs, digital adaptive equalizer (DAC), offset control unit, phase rotation matrix, controlled oscillator, reverse phase rotation matrix, two analyzing blocks, error signal conditioner, decoder, generator control unit, clock extraction unit (BBTA). discrambler, phase shifter, descrambler and byte synchronization unit. The goal is achieved by using the absolute modulation method in the device. In this method, the modulation on the transmission side is carried out in accordance with the information symbols currently being transmitted. In this case, the device eliminates the effect of the reverse operation, which occurs in the absolute modulation method. Examples of CAC and BVTK are given. 2 hp f-ly, 4 ill. (L y oo 4iik CO CD

Description

The invention relates to telecommunications and can be used in the equipment for the formation of the main digital channel.

The aim of the invention is to improve the noise immunity of data transmission.

FIG. 1 shows a structural electrical circuit of the transmitting side of the proposed device; in fig. 2 is a structural electrical circuit of the receiving side of the proposed device; in fig. 3 is a structural electrical circuit of a digital adaptive equalizer; in fig. 4 is a structural electrical block diagram of clock pulses.

The device for converting signals contains a generator 1, and on the transmitting side a switch 2, a scrambler 3, an encoder 4, the first and second generators 5 and 6 of the signal spectrum, the first and second modulators 7 and 8, an additional encoder 9, the first adder 50, . digital-to-analog converter 11, output matching unit 12, decoder 13, second and third adders 14 and 15, and on the receiving side - input matching unit 16 5 amplifier 17 with automatic gain control of AGC, first and second demodulators 18 and 19 convert to 20 Hilbert's first and second analog-to-digital converters (ADC) 21 and 22, digital adaptive equalizer 23, offset control unit 24, phase rotation matrix 25, controlled oscillator 26, reverse phase rotation matrix 27, first and second analyzing units 28 and 29 vimiro atel error signal 30, a decoder 31, a generator control unit 32, separation unit 33 clock oscillations descrambler 34 fazovraschaetl 35, decoder 36, the block 37 forming the byte timing.

The digital adaptive equalizer contains the first and second delay lines 38 and 39 with taps, the first and second adders 40 and 41, the logical unit formation unit 42, the first 43, the second 44, the third 45, the fourth 46, the fifth 47, the sixth 48, the seventh 49 tap regulators.

The clock selection unit comprises an adder 50, the first and second multipliers 51 and 52, the first and second blocks 53 and 54 of the power source, the first and second delay elements 55 and 56, the driver 57 also TOB6IX oscillations.

The device works as follows.

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The transmitted information in the form of a binary sequence arrives at scrambler 3. The purpose of scrambler 3 is to guarantee the pseudo-random nature of the transmitted signals necessary to prevent energy concentration in certain small parts of the range and to ensure proper operation of the receiving side. From the output of the scrambler 3, the information sequence arrives at the encoder 4, where the transmitted rto information is distributed to two subchannels

(T and Q), in each of which it is malformed and encoded according to the Quadrature Amplitude Modulation (QAM) method.

After encoder 4 signal

to each; the subchannel through the corresponding adders I4 and 15 enters the shapers 5 and 6 of the signal spectrum, which give the spectrum of transmitted signals a predetermined shape

(required rounding of the spectrum).

From the outputs of the formers 5 and 6 of the spectrum, the signals arrive at the corresponding modulators 7 and 8, where they are multiplied with the carrier oscillation generated in generator 1. In the R and Q subchannels, the carrier oscillations have the same frequency f, but differ in phase on, and the modulated signaling on the modulators of the modulators 7 and 8 in the cyr subchannels

they look like

R (t) cos and Q (t) sin.

Then, the modulated signals of the subchannels R and Q are combined in with the mapper 10.

After the adder 10, a digital signal having the form of samples of 1-bit numbers is converted into analogue form by means of a digital-to-analog converter (DAC) 11. From the output of the DAC 1, the signal goes through the output side of the transmitting side through the output matching unit 12. In the output matching unit 12, the signal spectrum is transferred to the required range (in the first channel - in the range 64–80 kHz, in the second channel - in the range 88 3

104 kHz) by oscillation coming from oscillator 1.

The device uses an absolute modulation method. With this method, the modulation on the transmitting side is carried out in accordance with the information symbols currently being transmitted (as opposed to the relative modulation method, in which the value of, for example, the signal phase at the considered moment depends on the previous state).

To eliminate the backward effect that occurs with the absolute modulation method, the device uses the following method

The signals from the outputs of the encoder A are fed to the first decoder 13, which from the total signal flow separates the signals with coordinates, for example, + 3 / + 3 (the first digit indicates the signal value by subchannel R, the second - by subchannel Q). The signal thus extracted is sent to an additional encoder 9, to the first input of which, through switch 2 from generator 1, a signal is received whose frequency is 8 times less than the frequency of arrival of information symbols. In the case of a coincidence of the pulse of the sequence from the output of the switch 2 with the signal position selected by the decoder 13, having the form of, for example, a logical unit, a signal is formed in the additional encoder 9, for example, with coordinates

The signal thus generated is fed to the formers 5 and 6 of the signal spectrum through the adders 14 and 15, in which, summing with the transmitted signal + 3 / + 3, is converted into a signal with coordinates + 4 / + 4. If the signal from the output of the decoder 13 does not coincide with the signal from the output of switch 2, a signal with O / O coordinates is sent to the encoder 9. In accordance with the considered principle, the transmitted, unchanged signal is transmitted to the inputs of the shaper 5 and 6 of the signal spectrum. The transmission signal generated in this way will be modulated by an absolute method.

The described generation of the absolute modulation method can be additionally used for transmitting byte (octet) synchronization.

49914

The presence of this type of synchronization is determined by the requirements for the hardware of the main digital channel. In this case, the sync input

5 device receives a byte synchronization signal from an external source. In this case, in the encoder 9, a signal + 1 / + 1 is formed in case of coincidence (in time) of signals with

0 output of the decoder 13 and byte sync synchronization coming through the switch 2.

The received signal arriving at the input of the receiving side, through

5 input matching unit 16 is supplied to the amplifier 17 with AGC. The AGC maintains the nominal output level of the signal when it changes at the input. The composition of the amplifier 17 with AGC

Q includes a converter switched on at the output of amplifier 17 and transferring the spectra of the signal of the first and second channels to a lower carrier frequency.

5 The demodulators 18 and 19 of the subchannels R and Q consist of series-connected multipliers to low-pass filters, used to suppress the conversion by-products resulting from demodulation, as well as to suppress the effects of the signal of another channel. In this case, the demodulating carriers coming from the generator 1 to the demodulators 18 and 19 are orthogonal to each other. This

 orthogonality is provided by the hilbert transducer 20.

After demodulation, the signals of the subchannels R and Q are fed to the A / D converters 21 and 22, the outputs of which are converted into digital form at the reference time points determined by the clock frequency (type of R-bit code combinations). Further, for the correction of intersymbol distortions caused by the non-ideal frequency characteristics of the communication channel, the signals are sent to a digital adaptive equalizer 23, which has a crossed structure that allows

adjust both bc (metric distortion in the subchannels R and Q, as well as asymmetrical distortion, the consequence of which is the mutual influence

between the signals of the subchannels R and Q. Next, through the phase rotation matrix 25, the signals arrive at the analyzing blocks 28 and 29, which of the signals

R o a, and I; form the estimates of these signals

 AU LS1

fishing; ive reference values tiHH closest to which (in terms of distance) is the signal.

Thus, in analyzing blocks 28 and 29, decisions are made on the value of the signal at the output of the phase rotation matrix 25. The signal estimates received from the outputs of the analyzing units 28 and 29 are decoded at the decoder 31 and converted into a binary sequence form having the frequency of the information symbols.

After the descrambler 34, the signal has the form of a transmitted information sequence of a given channel arriving at the output of the receiving side.

By comparing the signals at the input and output of each analyzing unit 28 and 29, error signal generator 1c and 1 Cyr subchannels are generated in the error signal generator 30:

R A “a. - but,

and

Y ((

LQ a; - aj

Ig error signals are used to generate signals that control the setting of the digital adaptive equalizer 12, as well as to control the phase rotation matrix 25 and the reverse phase rotation matrix 27.

The phase rotation matrix 25 and the phase rotation inverse matrix 27 together with the controlled generator 26 and the generator control unit 32 synchronize the device. In the controlled generator 26, sin 0 values are generated; and cos b ;, where 0; - the error in setting the phase of the signal, by means of which asynchronous demodulation is performed. In the phase rotation matrix 25, the distortion correction (compensation) is performed, caused by an error of 0; in carrier phase. The determination of the magnitude is carried out from the results of processing the received information signal in the generator control block 32. Demodulators 18 and 19, with this construction of the device, oscillate from generator 1 through phase shifter 35.

The inverse phase rotation matrix 27 included in the control circuit of the digital adaptive equalizer 23 is necessary for the digital adaptive equalizer 23 to work properly in the presence of carrier phase errors.

In order to carry out adjustment of the phase of clock oscillations, a block 33 for extracting clock oscillations is provided in the device.

The allocation of byte synchronization at the receiving side is carried out as follows.

The decoder 36 receives signals a. and a, from the output of the matrix 25 phase rotation. The decoder 36 selects the signals corresponding to the reception of a signal with coordinates + 4 / + 4. If the selected vector of the Torque with these coordinates corresponds to the transmitted vector, then the phase of the carrier oscillation at the reception is set ideally, if the selected vector of the signal is in another quadrant, then it is necessary to rotate the phase of the carrier oscillation by

 T ANGLE, equal m -, where m is the number of the quadrant in which the received signal is registered.

Since this signal must be located in the first quadrant, based on the signal about the quadrant number in the decoder 36, a control signal is generated to adjust the carrier oscillation by means of the phase shifter 35.

Claims (1)

Invention Formula 1, a device for converting signals containing a generator, and on the transmitting side a scrambler, the output of which is connected to the input of the encoder, the first and second signal conditioners of the signals whose outputs are connected to the first inputs of the first and second modulators, respectively, the outputs of which are connected respectively to the first and the second inputs of the first adder, the output of which through a digital-to-analog converter is connected to the first input of the output matching unit, the second input of which is connected to the first output of the generator , the second, third and fourth outputs of which are connected respectively to the second input of the first modulator, to the second input of the second modulator and to the second combined inputs of the first and second signal spectrum transmitters, and on the receiving side an input matching unit, the output of which is connected to the first an amplifier input with automatic gain control, the output of which is connected to the first inputs of the first and second demodulators, whose outputs are connected to the first inputs of the first and second analog-digital converters, respectively Applicants whose outputs are connected respectively to the first and second inputs of the digital adaptive equalizer, the first and second outputs of which are connected respectively to the first and second inputs of the phase rotation matrix, the first output of which is connected to the input of the first analyzing unit and the first input of the error signal conditioner, the second input which is connected to the second output of the phase rotation matrix and to the input of the second analyzing unit, the output of which is connected to the third input of the error signal generator, with the first input of the block In the clock division, with the first input of the generator control unit and the first input of the decoder, the second input of which is connected to the output of the first anaising unit, to the alternate input of the error signal generator, to the second input of the clock selection unit and to the second input of the generator control unit, third whose fourth inputs are connected to the third and fourth inputs of the clock extraction unit, respectively, to the first and second outputs, respectively, of the error signal and, respectively. The first and second inputs of the inverse phase rotation matrix, the first and second outputs of which are connected respectively to the first and second inputs of the offset control unit, the output of which is connected to the control input of the digital adaptive equalizer, the third output of which is connected to the third input of the offset control unit, clock input which is connected to the output of the clock extraction unit, to the second inputs of the first and second analog-digital converters, to the clock input of the descrambler and to the clock input of the decoder, the output of which is connected to the signal input of the descrambler, the output of the generator control unit is connected to the input of the controlled generator, the second input of the second demodulator is connected to the output of the Hilbert converter, the input of which is connected to the second input of the first demodulator and with the fifth output generator, the sixth output of which is connected to the second input of the amplifier with automatic gain control, characterized in that, in order to increase the noise immunity data transmissions, the second and third adders, a decoder, an additional encoder and a switch, the output of which is connected to the first input, are entered on the transmitting side additional encoder, the second input of which is connected to the output of the decoder, the first and second inputs of which are connected respectively to the first and second outputs of the encoder and to the first inputs of the second and third adders, respectively, the second inputs of which are connected to the output of the additional encoder, the outputs of the second and third summator are connected to the second inputs, respectively, of the first and second signal conditioners, the seventh generator output is connected to the first BXI switch house, and to the receiving station. A phase shifter, a decoder and a byte synchronization unit are added to the input, the input of which is connected to the first output of the decoder, the second output of which is connected to the first input of the phase shifter, the first output of which is connected to the third input of the phase rotation matrix, the first and second outputs of which are connected respectively to the first and second the decoder inputs, the output of the controlled oscillator is connected to the second input of the phase shifter, the second output of which is connected to the third input of the inverse phase rotation matrix. 2, The device according to claim 1, wherein the digital adaptive equalizer contains the first and second delay lines with taps, tap regulators, the first and second adders and the unit of formation of the logical unit, the first output which is connected to the input of the first tap controller, the output of which is connected to the first input of the first sum pa and to the outputs of the second regulators from the waters, the inputs of which are connected to the corresponding first outputs of the first delay line with the outlets, to the first inputs of the corresponding third regulators of the outlets and to the first corresponding outputs of the second delay line with the outlets, the third regulators the first adder and the output of the fourth tap controller, the input of which is connected to the second output of the second delay line with the tapes, the third outputs of which are connected to the inputs of the fifth corresponding regulators the leads whose outputs are connected to the first input of the second adder, the second input of which is connected to the outputs DiecTbDc of the tap controllers and the output of the seventh tap control, the input of which is connected to the second output of the logical unit forming unit, the second high voltage of the first delay line with the leads connected to the inputs the sixth tap controllers, while the control inputs of the first tap controller, the second tap controller, the third tap controller, the fourth tap controller, the fifth, sixth and seventh tap controller The control input of the digital adaptive equalizer, the first and second inputs of which are signal inputs of the first and second delay lines with taps, the outputs of the first  L.- KSffOKuT 9 K Ilonap 79, rO tpui.f 0 five 0 five 0 And the second adders, respectively, the first and second inputs of the digital adaptive equalizer, whose third output is the first outputs of the first delay line with taps and the first and second outputs of the second delay line with taps. 3. The device according to claim 1, about tl and - the fact that the block of separation of clock oscillations contains a clock oscillator, an adder, two multiplicators, two subtraction blocks and the first and second delay elements, the outputs of which are connected to the first inputs, respectively, of the first and second subtraction units, the outputs of which are connected to the first inputs of the first and second multiplication units, respectively, the outputs of which are connected to the first and second inputs of the adder, the output of which is connected to the input of the clock generator The oscillations, the inputs of the first and second delay elements are connected to the second inputs of the first and second subtractors, respectively, and are the first and second inputs of the clock selection unit, the third and fourth inputs of which are the second inputs of the first and second multipliers, respectively. The output of the clock oscillator is the output of the clock oscillator.