SU1223373A2 - Device for multiplexing transmission directions in duplex communication systems - Google Patents

Abstract

The invention relates to telecommunication technology and improves auth.St. No. 1133675. The noise immunity increases with changing parameters of the communication channel. The device contains an input unit 1, a switch 2, two digital-to-analog converters (DAC) 3, |, an analog-to-digital converter (DAC) 4,

Description

shaper address 5, two blocks 6, 10 memory, reHepatop 7 control pulses, subtractor 8, adder 9, block 12 of directing (WU), consisting of a source 13 of the reference voltage, shaper 14 of the adaptation interval, accumulating adder 15, trigger 16, two elements. The invention relates to a telecommunication technique, can be used in data transmission systems for dividing transmission directions, and is an improvement of the device according to the main auth. № 1133675.

The purpose of the invention is to increase the noise immunity with changing parameters of the communication channel.

The drawing shows the structure; The electrical circuit of the proposed device.

A device for dividing transmission directions in duplex communication systems comprises an input unit 1, a switch 2, a first digital-to-analog converter 3, an analog-digital converter 4, an address generator 5, a first memory block 6, a control pulse generator 7, a subtractor 8, an adder 9 , the second memory block 10, the second digital-to-analog converter 11, the control block 12, consisting of a 13-reference voltage source, an adaptation interval generator 14, an accumulator adder 15, a trigger 16, a first And 17 element, a reverse account ika 18, DAC 19 and the second AND gate 20, ny adaptive frequency divider 21, consisting of a counter 22, a threshold unit 23, latch 24, OR gate 25 and the unit 26 buffer memory.

The device works as follows.

The operation of the proposed device can be conditionally divided into the process of preliminary adaptation and the process of adaptive separation of signal transmission directions.

1223373

And 17, 20, reversible counter 18, DAC 19, adaptive frequency divider 21, consisting of counter 22, threshold unit 23, trigger 24, OR element 25 and buffer memory block 26. The goal is achieved by introducing the divider ADC 21 and BU 12. 2 Cp. f-ly, 1 ill.

The pre-adaptation process is no different from the adaptation process in the known device h as follows. The control signal from the data end equipment (not shown), supplied automatically or manually, goes to switch 2 and simultaneously to the second memory block 10. This signal zeroes the second memory block 10 and connects the output of the address driver 5 to the input of the first digital-to-analog converter 3 via switch 2. The address driver 5 is in digital form

- gives to the input of the first digital-to-analog converter 3 all used digital combinations: a, a, .. a. These digital combinations are converted by the first digital-to-analog converter 3 to voltages and ,,,, ... Uj, which are fed to the communication channel. At the same time, the indicated voltages are converted by analog-digital converter 4 into the corresponding digital combinations U (K, ut), U. (KjAt), ..., and "() and are written into the first memory block 6, and , is written U (), no to address a - UjCKjAt), to address a "- U (), where K :; - the current count number. This is where the pre-adaptation process ends with (Signal from the terminal equipment - data switch 2 connects the output of the input unit to the input of the first digital 5 analogue converter 3. At the same time, the output signal from the second memory unit 10 is removed. And in the process of pre-adaptation, the opposite side signals must be absent.

0

The process of adaptive separation of the transfer can be explained as follows.

Input unit 1 converts the incoming signal U; (t) into one of the code combinations aj. Suppose, for example, that the first time instant the input block I converts the incoming signal U (t) into the first digital combination a. This digital pattern is converted by the first digital-to-analog converter 3 to a signal U, which is fed to the opposite station. At the same time, a signal Y is received from the communication channel, and at the input of analog-digital converter 4 there is a sum signal G, and, + Y, which is converted by analog-digital converter 4 into digital form

ot: (K ,,, At) U, (K ,, t) -Hy, (K ,, ut) (l.)

and calculated at the first input, calculator 8 (where n is the number of the previous reference). Since a digital combination is transmitted to the opposite station, the contents of a h are output from the first memory block 6, the memory tags U () and the second input of the subtractor 8 are fed. At the output of the subtractor 8, the resulting signal looks like

M (K ,, 4t) “, (Kn ,, ut) -U, (K, 4t) Y, (K ,,, ut) + u ,, (2)

where D | and, (К „+, ut) - is the error -U, (к, it) compensation.

Moreover, U, (Kn +, it) and and, (k, At) -; signals characterizing the transmission of a digital combination a, at different (nft i K, ut) points in time. With constant parameters of the communication channel, the values of L i at the output of the pattern 8 have different values, not exceeding the quantization step of the analog-digital converter 4, and different signs.

The result of the subtraction from the output of the subtractor 8 is added to the contents of the memory cell of the second memory block 10 in the adder 9, thereby restoring the form of the received signal y (t), which is then converted in the second digital-to-analog converter 1 I. Thus, after the first clock at the output of the adder 9 will be the value

D (K ,, ut) M, (K ,,,, it) y, (K., 6tU

+ D;. (3)

After m ticks (where m is the number of ticks since the start of work) on

the output of the adder 9 will be the value

m

D (K ,, ut) yHK ,, ut) + Z: u, -. (h

till

The value of .51 L; fQ may be close to zero with constant channel parameters, or be different from zero with changing CB and channel parameters.

In order to eliminate the signal with a short, sensation, control unit 12 and an adaptive frequency divider 21 serve. Control unit 12 makes a decision about the presence of an undercompensation signal at the receiver input and gives the Q control signal for the new transmission conditions to the corresponding changes in the amplitude of the transmitter output signal.

For this purpose, the signals D; (K ut) are fed to the accumulating adder 15, 5, the output of which accumulates a signal with a value equal to

 g (h (; chy.

0: p. (. Ь | г / иЬч,., "

W. Where; rG - determines the error of under-, ° compensation; S-d. Determines the quantization noise error j t t i i i; L defines an error, is generated. -t7 J / i giving expression (5) giving the accepted signal for a large value (), it is not difficult to see that the sign of the sum Z (t) is op I l

  -

determined by the sign of i-uW ;,

IJM j. .

which in turn depends on

sign signal nedokompeisatsii. Thus, due to the random nature of the change of the Ziak and the size of the received signal and their quantization noise. mean close. Since the signal samples -uWj - have. the same sign, then for large N 0. i ti

s value. AWj is substantially larger.

values of the two dead terms. Therefore, the sign of the signal Z (t) is determined by the sign of the undercompensation signal, which, in turn, is determined by the direction of change of the communication channel parameters, for example, the input impedance modulus.

five

$ 1

The adaptation interval (the value of N) sets the shaper 14 adaptation interval, after which

I. :

the sign of Sgn from the first Y. 1

the output of accumulation of its adder 15 is fixed in trigger 16, and the absolute

value

n

.SIuW; R

J is fixed at

a buffer memory unit 26 for controlling the division ratio of the adaptive frequency divider 21.

The signals from the output of the trigger 16 (logical 1 or o) open the first element And 17 or the second element And 20 and pass to one of the inputs of the reversible counter 18 pulses from the output of the adaptive frequency divider 21. These pulses change the state of the reversible counter 18, thereby changing the code applied to the input of the digital-to-analog converter 19. The last converter 19 multiplies the reference signal from the output of the source 13 of the reference voltage and the digital combination from the output of the reversing counter 18. The output of the digital-analog converter 19 which is the reference signal for the first D / A converter 3, changes the amplitude of the transmitted samples in antiphase of change of the parameters of the communication channel. For example, if the input impedance ka, N

Nala communications increased then

has a positive sign. Logic 1 is fixed in trigger 16, the first element 17 is thus opened, and clock pulses are passed to the (-) input of the reversible counter 18, as a result, the output signal of the digital-to-analog converter 19 decreases, the reference voltage of the first digital-to-analog converter decreases

3. and output signals are decreasing.

 to

 as long as the value

.

Mr. J rt becomes equal to O.

To increase the convergence rate of the error signal compensation process, an adaptive frequency divider 21 serves. Output frequency adap223373 6

The frequency divider 21 is defined as

1-fJ ..W, |

(b)

for example, if

N

ten

.iWj | -20, Toi ,,,, - i ,, (l-,

what if

N

il-4. ,, nr / 2,

Where

BG is the specified clock frequency.

Thus, the larger the undercompensation value, the higher the clock frequency at the output of the adaptive frequency divider 21, which makes it possible to shorten the adaptation time.

By taking more ego work. The clock pulses from the output of the generator 7 are fed to the input of the counter 22, the IL element 25. The trigger 24 is in the initial (zero) state. In block 26 of the buffer memory

- - fixed value

Iftw

The threshold unit 23 compares the state of the counter 22 and the value

1 g

N,. -bW

From the output of block 26 of the buffer memory. As soon as the state of the counter 22 reaches the value of the state of the buffer memory block 26, the output of the threshold block 23 is a signal of the logical unit, which is recorded in the next (K + 1) -th clock in the trigger 24. The trigger 24 has zeroed the counter 22 , as a result, the signal from the output of the threshold block 23 enters, and the next (K + 2) -th clock cycle returns to the initial state. Thus, the trigger 24 is two clocks f j in a single state

I W -, on the interval iVJ, and thus for I J4

prevents f from passing through the output of the adaptive frequency divider 21.

Claims (3)

1. A device for dividing transmission directions in duplex communication systems according to auth. No. 1133675, characterized in that. in order to improve the noise immunity of the device with changing parameters of the communication channel, an adaptive frequency divider and a control unit are introduced into it, the first, second and third outputs of which are connected - respectively to the auxiliary input of the first digital-to-analog converter and to the first and second inputs of the adaptive frequency divider, the output of which is connected to the first input of the control unit, the second and third inputs of which are connected respectively to the output of the adder and the output of the generator of control pulses, which The key to the third input of the adaptive frequency divider. 2. The device according to claim I, characterized in that the adaptive frequency divider comprises a buffer memory block and a sequentially connected counter, a threshold block, a trigger and an OR element, the second input of which is connected to the first input of the counter, to the second input of which the trigger output is connected, the second input of which is connected to the second inlet of the OR element, the output of which is the output of the adaptive frequency divider, the first, second and third turns of which are, respectively, the inputs of the buffer memory block. Compiled by A.Moskevich Editor O. Bugir Tehred O. Gortvay Order 1725/59 Circulation 624 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35. Raushsk nab. 4/5 Branch PPP Patent, Uzhgorod, st. Project, 4 23373 8 the output of which is connected to the second input of the threshold unit, and the first input of the counter. , 3. The device according to claim 1, characterized in that the control unit comprises a series-connected reference voltage source and a digital-analogue converter, the first AND element and the series-connected shaper of the adaptation interval, the accumulator. the adder, the trigger, the second element And the reversible counter, the second 15 input and output of which are connected respectively to the output of the first element And, to the first input of which the second output of the trigger is connected, and to the second input of the digital-analogue 20 of the converter, the output of which, the output of the adaption interval former and the second output of the accumulating adder are respectively the first, second and third outputs 25: control unit, nepBwi, the second and third inputs of which are respectively a second input of the first element AND, which is connected to the second input of the second element And, secondly The 30th entrance of the accumulating accumulator and the input of the adaption interval: tation generator. .: Proofreader G. Reshetnik