SU1223289A1 - Device for magnetic recording-reproducing of digital information - Google Patents

Abstract

The invention relates to magnetic recording, in particular, to devices for magnetic recording-reproduction of digital information. A binary number supplied via the input information buses 2 is recorded in the first register 1 by a tracking signal received via the input control bus 12. At the same time, a follow-up signal resets trigger 26 and sets trigger 25 to one. The trigger 25 connects the digital-to-analog converter 3 to the integrator 18, which generates a voltage drop, the slope of which is determined by the binary number in the first register 1. The integrator 18, through the recording amplifier 7, acts on the magnetic recording head 4, which provides magnetization of the magnetic recording medium 6. The integrator 18 also provides the triggering of the comparator 19 acting on the one-shot 20, the latter generating a pulse, which, via the delay element 21, sets the trigger 25 to the zero state. The trigger 25 provides a connection to the integrator 18 of the source 35 of the reference voltage. The reproduction part of one of the possible variants of the device is also described. 2 Il. § (L 17 18

Description

The invention relates to the field of magnetic recording, in particular, to devices for magnetic recording-reproduction of digital information.

The purpose of the invention is to increase the reliability of reproduction of digital information.

FIG. and 2 depicts the recording and reproducing parts of the proposed device for magnetic recording of digital information.

The device contains the first register 1 connected between the input bus 2 information and the inputs of the digital-to-analog converter 3, recording and reproducing magnetic heads 4 and 5, mounted with the ability to interact with the magnetic recording medium 6 and connected respectively to the input of the recording amplifier 7 and with the input of the playback amplifier 8, the second register 9, the shaper -10 clock pulses, the output information 11, the first and second input buses 12 and 13 of the control signals and the output bus 14 of the control signal. In this case, the output of the playback amplifier 8 is connected to the information input 15 of the analog-digital converter 16.

The device also includes a switch 17 connected in series and an integrator 18 connected by a output to the input of amplifier 7, connected in series the first comparator 19, the first one-shot 20 and the first delay element 21, connected in turn by the second comparator 22 the second one-shot 23 and the second delay 24, the first and the second trigger 25 and 26, the element NOT 27, the first, second and third amplifiers 28-30, the first, second and third elements. AND 31-333, the peak detector 34 and the source 35 of the reference voltage. The input element 27 is connected to the output of the clock clock 10, connected to the reference input 36 of the analog-digital converter 16, to the output bus 14 of the control signal and to the input of the second register 9, the second register 9 is connected between the outputs of the analog-digital converter 16 and 11 output tire information. The first trigger 25 is connected to the input of the installation of the logical unit and the first input of the installation

logic zero to the first and second input buses 12 and 13 of the control signals. The second trigger 26 is provided with an additional output control signal bus 37 connected to its output. The input of the first amplifier 28 is connected to the output of the playback amplifier 8, which is connected to the input of the driver 10 clock pulses.

The output of the second amplifier 29 is connected to the input 38 of the reset analog-to-digital converter 16. The integrator 18 is connected to the inputs of the first and second comparators 19 and 22. yakhod

a digital-to-analog converter 3 is connected to the first input of the switch 17 connected by a second input to the output of the source 35 of the reference voltage and connected by the third input

to the output of the first trigger 25. The first trigger 25 is connected to the second input of the installation of logical zero with the output of the first element 21 of the delay. The output of the second delay element 24 is connected to the input of the installation of the logical unit of the second trigger 26, sub-j of the single input of the installation of logical zero to the output of the first register 1. The output of the driver 10 clocks

pulses connected to the first input of the first element And 31 and to the first input of the second element And 32, the output of which is connected to the first memory element 39 and to the input of the second

the amplifier 29. The second input of the second element And 32 is connected to the output of the third amplifier 30. The output of the first amplifier 28 is connected to the second input of the first element And 31 connected by the output to the input of the peak detector 34. The output of the peak detector 34 is connected to the second memory element 40, c the input of the third amplifier 30 and with the first input of the third

element And 33, connected by a second input to the output of the element NOT 27 and connected by an output to the common bus. In this case, the first and second elements 39 and 40 of the memory are executed in the form

capacitors connected to a common bus. .

Analog-to-digital converter 16 consists of a converter of 41 codes, of register 42, of comparators 43 and of resistors 44. The first inputs of comparators 43 coincide with the information input of 15 analog-digital converter 16. Vto20

25

The other inputs of the comparators 43 are connected to resistors 44 connected in series between the common bus and the reference input 36 of the analog-digital converter 16. The outputs of the comparators 5 are connected to the inputs of the register 42 connected to the inputs of the converter 41 codes and to the input 38 of the analog-digital reset converter 16. The converter outputs 10 41 codes coincide with the outputs of the analog-digital converter 16.

Magnetic recording-reproduction of digital information through the proposed device is as follows,

In the initial state, the first trigger 25 is in the one state, and the second trigger 26 is in the zero state. The integrator 18 is in the saturation state. Before starting the recording, the signal received via the second input bus 13 of the control signal sets

The first trigger 25 to the zero state and connects to the integrator 18 a source 35 of the reference voltage. The integrator 18 generates a voltage drop acting through the recording amplifier 7 on the recording magnetic head 4 and triggers the second comparator 22 acting on the second one-oscillator 23. The second one-oscillator 23 generates a pulse, which through the second element 35

The 24 delay sets the second trigger 26 to the one state. The second trigger 26 generates a data readiness signal, which is fed to the additional output bus 37 of the control signal. The binary number supplied via the input information buses 2 is recorded in the first register 1 by the tracking signal received via the first input bus 12 of the control signal. One time signal for the tracking signal resets the second trigger 26 and sets the first trigger 25 to one. The first trigger 25 connects the -50 digital-to-analog converter 3 to the integrator 18. The integrator 18 forms another voltage drop, the slope of which is determined by the number in the first register 1. The integrator 55 18 through the recording amplifier 7 acts on the recording magnetic head 4, providing a magnetizer

thirty

40

45

media 6 magnetic recording. In this case, the integrator 18 also triggers the operation of the first comparator 19 acting on the first single vibrator 20. The first one-shot 20 produces a pulse, which, through the first delay element 2I, sets the first trigger 25 to the zero state. The first trigger 25 provides a connection to the integrator 18 of the source 35 of the reference voltage,

In the playback mode, the reproducing magnetic head 5 acts through the reproduction amplifier 8 on the first amplifier 28, on the analog-digital converter 16.

Lormior 0 clock pulses. The pulse shaper 10 clocks opens the first and second elements AND 31 and 32, respectively, for the voltages of the first and third amplifiers 28 and 30. Due to this, the voltage of the peak detector 34 is memorized by the second memory element 40, and the third voltage of the third amplifier 30 memory The antiphase pulse of the clock maker 10 closes the first and second elements 3 and 32 and opens the third element 33 through the NOT 27 element and discharges the second memory element 40. The voltage from the output of the second amplifier 29 is supplied to the analog-to-digital converter 16 ,. providing a discretization of the subsequent pulse. In the analog-digital converter 16, the spatial code obtained using comparators 43 is entered into a register 42 acting on the code converter 41. The binary code from the output of the analog-to-digital converter 16 by the positive differential pulse of the driver 10 clock pulses is written to the second register 9 and is fed to the output information bus 11.

Claims (1)

Formula and goiter shade A device for magnetic recording and reproduction of digital information containing a first register connected between input information buses and inputs of a digital-to-analog converter, recording and reproducing magnetic heads mounted with interaction with a magnetic recording carrier and connected respectively to the output of the recording amplifier and with the input of the playback amplifier connected by the output to the information input of the analog-digital converter, the second register, the shaper of clock pulses information output busses, the first and second control signal input buses and the control signal output bus, characterized in that in order to increase the reliability of digital information playback, a switch and integrator connected in series are connected to the input of the recording amplifier, connected in series the first comparator, the first one-shot and the first delay element, connected by a series of the second comparator, the second one-20 is connected to the input of the logical rator and second delay element, NOT element, connected by an input to the output of the clock pulse generator, connected to the reference input of the analog-digital converter, to the output bus of the control signal and to the input of the second register connected between the outputs of the analog-digital converter and output buses information, the first trigger connected to the installation input of the logical unit and the first installation input of the logical zero to the first and second input control signal buses. 25 thirty units of the second trigger connected by the logical zero input to the output of the first register, clock generator output. connected to the first input of the first element And to the first input of the second element And connected by the second input to the output of the third amplifier and connected to the first memory element and with the input of the second amplifier, and the output of the first amplifier is connected to the second input of the first element And connected by a junction to the input of the peak detector, the output the second trigger equipped with a connected- 5 of which is connected to the second element By connecting to its output with an additional output bus of the control signal, the first amplifier connected by the input to the output of the playback amplifier is connected to the 4 4Q input. memory, with the input of the third amplifier and the first input of the third .I element, connected by the second input to the output of the element NO. world clock clock, a second amplifier connected by the output to the reset input of the analog-digital converter, the third amplifier, 5, the first, second and third elements And, the first and second memory elements, the first-first detector and the source of the reference voltage, the integrator output being connected to the inputs of the first and second 10 comparators, the output of a digital-to-analog converter is connected to the first input of a switch connected by a second input to the output of a reference voltage source and connected 15th by a third input to the output of the first trigger, the second input of setting the logical zero of which is connected to the output of the first delay element units of the second trigger connected by the logical zero input to the output of the first register, the clock generator output is connected to the first input of the first element And to the first input of the second element And connected by the second input to the output of the third amplifier and connected to the output of the first memory element and the input of the second amplifier, and the output of the first amplifier is connected to the second input of the first element And connected by an output to the input of the peak detector, the output which is connected to the second element memory, with the input of the third amplifier and the first input of the third .I element, connected by the second input to the output of the element NO. Editor S.Patrusheva Compiled by Y.-K.V. Rosencrantz Tehred I.Popovich Proofreader E.Roschko Order 1720/55 Circulation 543Subscription VNIIPI USSR State Committee for Inventions and Discoveries 4/5, Moscow, Zh-35, Raushsk nab. 113035 Branch ShSh Patent, Uzhgorod, st. Project, 4 FIG. 2