SU1223237A1 - Multichannel interface for linking using equipment with common bus - Google Patents

Abstract

The invention relates to computing and can be applied in multi-machine and multiprocessor computer systems with more than three subscribers, using a twisted trunk for data exchange. The aim of the invention is to improve the performance of the entire computing system. Due to the ring connection of the devices and the logic of the device operation, the entire ring chain of the connection is divided into sections covering the source and receiver communicated with the minimum number of intermediate devices not participating in the exchange. Thus, the remaining subscribers, we are freed from the unproductive expectation of the release of the entire common highway. The device contains a maximum code generation unit, two key blocks, three registers, four groups of AND elements, an amplifier, a group of amplifiers, a trigger chip, four AND elements, seven OR elements, three NOT elements, three delay elements. 4 il. i SL y ts5 from to 00 J

Description

The invention relates to computing and can be applied in multi-machine and multiprocessor computer systems with more than three subscribers, using a common trunk for data exchange.

The aim of the invention is to increase productivity by eliminating the waiting time of unoccupied subscribers.

Figure 1 shows a block diagram of a device (an example for a four-machine system) in Figure 2 is a block diagram of a maximum code generation unit (an example for a four-bit priority code); in FIG. 3, the type of code; priority; 4 is a block diagram of a computing system.

The scheme contains channels 1, each of which contains a bus 2 ban, bus 3 requests, bus 4 answers, bus 5 synchronization, registers 6 - 8, triggers 9 - 12, information bus 13, a group of 14 elements And, elements 15 and 16, OR 17 element, comparison node 18, AND 19 element, code input group 20, AND 21 element, delay element 22, single pulse generator 23, AND 24 element, NOT 25 element, OR element 26 AND element 27, delay element 28, element OR 29, a group of 30 elements AND, a block 31 of bidirectional keys, a group of 32 elements AND, elements OR 33 - 35, a group of 36 elements AND, a block 37 d unidirectional keys, element I UTO 38, output 39 of the output end, group of code inputs 40, groups of outputs 41, start of steps, group of outputs 42, start of reception, group of information inputs-outputs 43, clock input-output 44, amplifier 45, group of amplifiers 46, the group of inputs 47 of the maximum code generation unit, the input 48 of the maximum code generation unit, delay element 49, signal output 50, interlock output 51, interlock input 52, maximum code generation block 53 containing AND 54, priority allocation sections 55, each of the otorrhea comprises an OR gate 56, NOT element 57, and elements 58 and the keys 59. The keys blocks may be performed, for example, triode

symmetric non-lockable thyristors (semistors). If there is a logical unity and | 3 a key on the control input of the key block of the signal, i.e. their first inputs / outputs are connected to their second inputs / outputs, and the keys pass signals in both directions. If a logical zero signal is set at the control input, the keys are closed, i.e. their first inputs-outputs are disconnected from their second in-outlets.

If all channels, starting with this one, are numbered in order against

clockwise (i.e., K 1, where K is the number of this channel), then the N-th output of the group of 30 elements I (dn H -K “E (M / 2), where E (X) is a function of the integer X ; M - the number of devices

in the closed circuit and H - the number of the interacting channel) K-go ka: 1 1 is connected to the corresponding input of the element OR 34 and through a group of amplifiers 46 with the corresponding

bus circuit 3 requests, and the N-th output of the group of 30 elements And (for H - K

 E (M / 2) of the K-th channel is connected to the corresponding input of the element OR 38 and through a group of amplifiers 46

with the corresponding bus circuit 3 requests. Bus circuits 3 requests K-th channel corresponding to the N-th channel (for H - K D (M / 2) + 1, where K 1, K is the number of this channel, and H is the number of the interacting channel) are connected by the inputs of the corresponding . elements And a group of 36 elements And, and the outputs of these elements And are connected to the corresponding inputs of the

The 38th Kth channel, the bus circuit 3 of the Kth channel requests corresponding to the Nth channels. (for H – E (M / 2) + + 1) are connected to the inputs of the corresponding And group elements 36

elements And, and the outputs of these elements And - with the corresponding inputs of the element OR 34 K-th channel.

The device works as follows.

The device is part of a computer system (figure 4) containing several channels C, Ij, ... f connected in a ring, one subscriber of the system is connected to each channel, for example a computer (subscribers are not shown in figure 4).

In the initial state on the information bus 13, the bus 3 requests

3

and the 4 response bus of each channel 1 is set to zero code, on the prohibition circuit 2 and the synchronization circuit 5 of each channel 1 logic zeros, registers 6-8, triggers are set. 9-12 of each channel 1 are in the zero state, the keys of the block 31 keys of each channel 1 are open, i.e. the first inputs-outputs of the keys of the block 31 of the keys of all channels 1 are connected to the second inputs-outputs of the same keys; therefore, the information buses 13, prohibition chains 2, synchronization chains 5, query buses 3 and 4 answers of all channels 1 form a single ring trunk, blocks The 37 keys of all channels 1 are closed, at the signal output 50 of all channels 1 a logical zero is set. At random points in time when there is a logical zero on the signal output 50 of channel 1, the device’s subscribers (for example, a computer), as necessary, to send messages to other subscribers, with a paraphase code on code input groups 40, the position codes of subscriber numbers for which the generated information is intended inputs 20 - priority codes. The priority code (FIG. 3) consists of the priority code of the information (message array) prepared for the subscriber and the source priority code. The source priority code determines the importance of the subscriber who prepared the information, and the priority code of the information determines its importance. When setting up a computing system, source priority codes can be changed on the fly, but they cannot be the same for any two subscribers at a given time.

Subscribers accessing channels 1 for information will be called source subscribers, and subscribers to whom this information is intended will be called receiver subscribers (in the same way we will call channels). Next, we consider the operation of one pair of channels 1, since in the other channels the operation is carried out in a similar way.

Consider channel I, to which the source subscriber is connected, will be called Km channel 1, and the remaining channels 1 are numbered, starting with the one under consideration (i.e. K 1),

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order counterclockwise (figure 4) and we will call the nth channel 1, to which the subscriber-receiver is connected. The priority code is written to register 6, and the code of the subscriber-receiver number, the number of bits in which is M-1 (where M is the number of channels in the computing system), is written to register 8. Since the group

Q 14 elements AND open, since their first inputs are supplied with a logical unit from the code of the element NOT 15 (a logical zero is set at its input), and the second inputs

j is a logical unit from the output of the NOT 16 element (since the input of the NOT 16 element is supplied from the output of the RSHI element 7 logical zero), then the priority code is written to pe2Q horn 7 and from its outputs goes to the group of inputs 47 of the maximum code generation unit 53 and on the first group of inputs of the node 18 comparison. The highest bit of the priority code corresponds to the first bit of the priority code of the information. Since the priority codes of all sources are different, different kodak is sent to the groups of inputs 47 of blocks 53 of different channels 1 Since a logical unit is installed at input 48 of block 53, it starts working (at zero on this input, block 53 is disconnected from the information bus 13). The code is formed on the information bus 13 sequentially, starting from the highest bit. If in the high-order priority code, a logical one is present in the group of inputs 47 of block 53,

 This triggers element 59 of the block, 53, with the result that a logical unit signal appears on the first circuit of the information bus 13. It is assumed that each of the circuits of the information bus 13 implements the wired OR fsgnation with respect to the signals of logical units, i.e. a logical unit, formed, for example, by AND 594, is transmitted to the circuit regardless of the state of the outputs of similar AND elements located in other channels 1.

Thus, on the first chain, all those units of units 53, y

55 of which there is a logical unit at the input of the higher bit. Blocks 53, which have logs-30 on the inputs of the senior bits.

50

cic zeros They do not upset the competitive struggle and are disconnected from the information bus, since the signal of the logical unit from the other blocks 53 is inverted by the HE element 57. At the output of the element OR 56, a logical zero is formed, which shuts down through the element 58 and the subsequent nodes 55 and the element 54. If none of the blocks 53 received the signal of the logical unit as the input of the higher bit, then the first circuit of the information bus 13 is present the signal of logical zero, which, having passed through the element NOT 57,, in the form of a logical unit, passes through the element OR 56, and together with the single signal at input 48 opens the start input of the next bit.

Thus, under paBHte conditions in the higher order, the struggle is transferred to the next discharge and after the time the system calms down (previously known and calculated by the worst case in the design) on the information bus 13, the maximum of the codes posting to the 47 inputs 53 different 53 channels 1. For example, if the codes arriving at groups of inputs 47 blocks 53 of three different channels 1 are: 1110, 1001, ITO, and the other channels 1 of the exchange request device are not received, then the information bus 13 is set to code 1110 . This code goes to the second input group of the comparison node 18 and in that channel 1, in which the identical input code is set on the first input group of the comparison node 18 (for example, in the Kth channel), a single signal comes from the output of the comparison node 18 and the first element And 19, to the second input of which a single signal is received through the delay time of element 22, calculated for the time to calm the system, since the output of element OR 17 results in a single signal at the moment when a logical unit signal appears on one of the circuits of the information bus 13. The third input element And 19 from the output element NOT 15 receives a logical zero signal.

Thus, a signal appears on AND 19, which sets the trigger 10 into one state and triggers the oscillator 23 one

five

0

five

0

five

0

five

S

night pulse. After the priority code appears on the information bus 13, the group 14 of the elements AND is closed, since its second inputs receive a logical zero signal from the output of the NOT element 16, the input of which from the output of the OR element 17 receives the signal of the logical unit. This prevents the change of the codes on the groups of inputs 47 of the blocks 53 to the time of the formation of the maximum code on the information bus 13. The signal from the single output of the trigger 10 establishes a logical unit on the circuit 2 of the device and the signal output of the 50th K channel. The signal of the logical unit, the passage through the element NOT 15, turns off the maximum code generation block 53, closes the elements AND 19 and 24 and the group 14 of elements I. A single signal from the output of the generator 23 of a single impulse opens the block 30 of elements AND. , closing, therefore, the group of 36 elements And, and through the amplifier 43 to the bus circuit of 3 requests corresponding to the given channel. At the N-m output of a group of 30 elements, And, a signal of a logical unit is received, which, through the corresponding amplifier of group 46, goes to the N-th bus circuit of 3 queries.

Since the proposed device has a ring structure, information is transmitted from the source subscriber to the receiver subscriber along the shortest path, i.e. in the direction where fewer channels are connected between the source subscriber and the receiver subscriber. Consider two cases. In the first case, the release of information occurs in the right direction relative to the source channel, i.e. the number of the receiving channel - N satisfies the condition H - K E (M / 2) (where K 1 and K jt H). Then the signal from the N-th output of the group of 30 elements And goes through the element, OR 34 to the single input of the trigger 9, and the logical zero signal from the zero output of this trigger through the element And 21 shuts down the key block 31, disabling the first inputs-outputs of the keys of this key block from their second inputs / outputs. A single signal from the bus circuit of 3 requests corresponding to the number of channel 1 - the receiver, from-;

7

Crush a group of 36 elements AND channel 1 - the receiver, entering their first inputs. The second input element And corresponding to channel 1 - the source, a group of 36 elements AND channel 1 -. Receiver receives a single signal from the bus circuit 3 requests, corresponding to channel 1 - the source, at the output of this element. And a single signal appears at the corresponding inputs of the elements OR 38 and 35 and at the corresponding output of the group 42 of the beginning of the reception of channel 1 - the receiver. On this signal, the subscriber-receiver terminates the execution of the current program and switches to the mode of receiving information from the corresponding subscriber-source. A single signal from the output of the element OR 38 channel 1 - the receiver is fed to the single input of the trigger 12 of this channel. The signal of logical zero from the zero output of the trigger 12 of channel 1 - the receiver arrives at the output 51 of this channel and through the input 52 of the (H + 1) -th channel closes the AND 2J element (H + 1) -th channel 1 (H - channel number 1 - receiver) and, therefore, the block 31 of keys (H + 1) -th channel 1 is closed. From this point on, the channels 1 can work, located outside the designated trunk section (between the source channel and the receiver channel), since for them on the line 2 prohibition the logical zero signal is set.

The signal of the logical unit from the output of the element OR 35 of the receiving channel through the element OR 33 of this channel sets the trigger I1 of this channel to one, and the signal of the logical unit from its single output opens the block 37 of the keys of the receiving channel. The signal of the logical unit from the output of the element OR 35 of the receiving channel through the circuit corresponding to this channel, the 4 response bus goes to the first input of the AND element corresponding to the receiving channel, the group of 32 elements And source channel and from its output goes to the corresponding output of the output group 41 start issuing the source channel, signaling the source subscriber about the need to issue through the delay time, due to the time the element OR 33 is triggered, trigger 11 and block 37

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keys, prepared information to the corresponding subscriber-receiver. The signal of the logical unit from the output element And, the corresponding channel of the receiver, a group of 32 elements And

source channel through the element OR 33 sets the trigger 11 of the source channel to one, the signal from its zero output closes

0 element And 27, and the signal from its single output opens the block 37 of the source channel keys, the first group of inputs-outputs 43 and the synchronization input-output 44 are received

J2, respectively, messages and clock pulses from the source subscriber. These messages and clock pulses from the second group of inputs-outputs of the block of 37 keys

20 source channels, respectively, through the information bus 13 and the synchronization circuit 5 are received via the block 37 of the channel-receiver keys, respectively, to a group of information

25 inputs and outputs 43 and. sync input-output 44 of the channel-receiver. After all messages have been issued, the source subscriber sends to the input 39 an end-of-issue signal that sets the source channel register 6 to the zero state and through the OR element 26 the register 7 and the source channel triggers 9-11. The trigger 10 sets on the circuit 2 of the ban signal of the logical zero, the signal of the logical unit from the zero output of the trigger 9 of the source channel arrives at the second input of the source element 21 of the source channel and, if the signal of the logical unit is present at its first input (the neighboring channel 1 is not occupied information exchange), then the source channel key block 31 is cleared, the logical zero signal from the single output of the source channel trigger 11 closes the key block 37 of this channel. When the source channel has set a logical zero signal in the interdiction circuit 2, a logical unit signal appears at the output channel And 24 in the receiver channel, since its first input is set to a logical unit signal from the output of the HE element 15, and the second input is also set to a logical unit signal, 55 which steps from the output of the delay element 49, whose input is connected to the interdiction circuit 2. The signal of the logical unit from the output element And 24 in

thirty

35

40

45

50

the receiver channel through the OR element 26 sets the triggers 11 and 12 to the zero state. The logical zero signal from the trigger 11 output of the channel-, the receiver blocks the key block 37 of this channel, and the logical unit signal from the zero output of the trigger 12 of this channel goes to the first input element 21 of the next channel and, if a logical unit signal is set at its first input (barely; next channel 1 is not engaged in information exchange), the block 31 of keys of the next channel is opened.

Thus, the device goes back to its original state if information is not exchanged between subscribers on other parts of the trunk.

In the course of further work, if, after the delay time of the delay element 28 after channel 1 - the source of the request (logical unit) on one of the bus lines of the 3 requests, no response was received, which indicates that channel 1 - the receiver is either serviced located on the blocked section (between exchanging channels) a single signal from the output of delay element 28, to the input of which a single signal from the output of element OR 29 arrives, to one of the inputs of which receives a single signal from one of the outputs of group 30 elect And, through AND 27, which is open, since the trigger 11 is in the zero state, through the OR element 26 it sets the triggers 9jlO and the register 7 is in the zero state and the source channel resumes the attempt to establish communication with the receiving channel, the subscriber is the source, receiving a logical zero signal from output 50 ,. can. change the contents of registers 6 and 8.

Let us now consider the differences in the operation of channel 1 in the case when information is transmitted to the left side relative to the source channel, i.e. when the number of the receiving channel - H satisfies the condition: H - K E (M / 2) + 1 (where K 1 and K i H). In this case, in the source channel, the signal of the logical unit from the H th output of the group of 30 elements AND through the element OR 38 (and not through OR 34, as it was in the previous case) will set the trigger

0

five

12 into one state, and the signal from its zero output through the next channel element 21 will close the key block 31 of the next channel. In the source channel, the signal of the logical unit from the H th output of the group of 30 elements I, passes through the corresponding amplifier of group 46, goes to the corresponding bus line 3 requests and, passing through the corresponding key of the key block 31, goes through the corresponding bus lines 3 requests of previous channels 1 (if between the source channel and

, the receiving channel has other channels) and their blocks of 31 keys to the corresponding bus line 3 requests of the receiving channel, and from it to the first input of the And element corresponding to the source channel of the 36 elements of the And receiving channel, the second input of which A single signal from the circuit corresponding to the number of the source channel, bus 3 requests the source channel arrives along a similar path, and a single signal from its output through the OR 34 element (and i not OR 38) sets trigger one (1) and the trigger 9 a) receiver channel, and zero. the signal from the zero output of this trigger through the element And 21 shuts down the block 31 of the keys of the channel-receiver. Otherwise, the operation of the device is repeated.

Thus, the proposed device allows, during the exchange process, to divide the common trunk into sections in which simultaneous data exchange is possible.

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Claims (1)

Invention Formula A multichannel device for interfacing subscribers with a common trunk, containing in each channel a block for generating a maximum code, a first trigger, two groups of AND elements, two registers, three NOT elements, two AND elements, a comparison node, two OR elements, a delay element, and groups and the information I / O of the maximum code generation unit is connected to the information bus line, a group of 5 information inputs of the first register is connected to the output group of the priority subscriber code of the corresponding subscriber, a reset input p the first- regi0 five five 0 h The country is connected to the output of the transfer terminal end. The first group of inputs of the comparison node and the group of inputs of the first element OR are connected to the information bus of the trunk, the input of the first element is NOT connected to the trunk inhibit circuit, while the group of information outputs of the first register is connected to the corresponding the first inputs of elements I of the first group, the outputs of which are connected to the group of information inputs of the second register, the group of information outputs of which are connected to the group of information inputs of the block the formation of the maximum code and the second group of inputs of the comparison node, the output of which is connected to the first input of the first element AND, the second input of which is connected to the output of the first delay element, the input of which is connected to the output of the first OR element and the input of the second element NOT whose output is connected to the second inputs of elements AND of the first group, the third inputs of which are connected to the output of the first element NOT, the enabling input of the maximum code generation unit, the first input of the second element AND, the third input of the first ele The input AND, the output of which is connected to the single input of the first trigger, which differs in that, in order to increase performance by eliminating the waiting time of unused subscribers, two blocks of bidirectional switches, an amplifier, five OR elements, a trigger, a register, two delay elements, two elements And, a group of amplifiers, a generator of a single pulse and two groups of elements And, with the output of the first trigger connected to the signal input of the corresponding subscriber and the trunk bar, the group of information inputs in the third register it is connected to the group of address outputs of the corresponding subscriber; the outputs of the elements of the second group are connected to the secondary inputs of the second element OR and connected to the input group of the beginning of the corresponding subscriber; the outputs of the first and second subgroups of the AND elements Tj5e5 of the subscriber, the first group of information inputs and outputs of the first block of bidirectional keys23237 12 ten 15 20 25 whose is connected to the group of information inputs-outputs of the corresponding subscriber, the first information input-output of the first block of bidirectional keys is connected to the synchronization input-output of the corresponding subscriber, the output of the amplifier and the group of outputs of the amplifiers of the group are connected to the trunk request bus, the first inputs And the second group of elements and the output of the third element of the SHS are connected to the bus response lines, the first inputs and the combined second inputs of the elements AND the third group are connected to the bus query lines, the second group The information input-output of the first block of bidirectional keys is connected to the information bus of the trunk, the second information input-output of the first block of bidirectional keys is connected to the trunk synchronization bus, the first input of the third element I is the device lock input, the zero output of the second trigger is device lock , the first group of information inputs and outputs of the second block of bidirectional keys is connected via the information bus, the request and response buses, the inhibit bus and synchronization of the trunk to the second group of information inputs and outputs of the second block of bidirectional keys of the subsequent channel, while 35, the control input of the second block of bidirectional keys is connected to the output of the third element I, the second input of which is connected to the zero output of the third trigger, the zero input of which is connected to the zero inputs of the first, second, fourth triggers, second register and output of the fourth element: SH, first the input of which is connected to the reset input 5 of the first register, the single input of the third trigger is connected to the output of the fifth OR element, the first group of inputs of which is connected to the first group of inputs of the sixth power amplifier ment Hilti and outputs the first subset of elements and a fourth group, the outputs of the second subset of elements, and fourth groups are connected to the second group 55 inputs of amplifiers of the group, the sixth OR element and the first group of inputs of the seventh ШШ element, the second group of which is connected to the second 30 outputs 40 50 13 a group of subgroups of elements of the third group and the first group of inputs a third of its element OR, the second group of inputs of which is connected to the second group of inputs of the fifth element OR and the outputs of the first subgroup of elements AND of the third group, the third inputs of which are connected to the output of the third element NOT, the input of which is connected to the input of the amplifier, the second inputs of elements AND of the second group, the first inputs of elements AND of the fourth group, the output of the generator of a single pulse, whose input connected to the output of the first element And, the third input of which is connected to the output of the fourth element And, the first input of which is connected to the output of the third 223237 element 14 entrance which .ten 15 delays connected to the output of the sixth OR element, the output of the third OR element is connected to the input of the second element. OR, the output of which is connected to the single input of the fourth trigger, the zero output of which is connected to the second input of the fourth element AND, the group of information outputs of the third register is connected. with the second inputs of elements AND of the fourth group, the single output of the fourth trigger is connected to the control input of the first block of bidirectional keys, the output of the seventh element OR is connected to the single input of the second trigger. go FIG. f IP $ 8t I 56i 59i 55A 2p 55, s2 S5 P 5ff fig z Uftgjop priority code Xr Source priority code FIG. 3 1m-l Fy Compiled by S. Pestmal Editor A. Shandor Tehred L. Oleinik Order 1715/52 Circulation. 671Subscribe VNISh State Committee of the USSR for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Branch PPP Patent, Uzhgorod, Proektna St., 4 Proofreader O. Lugovay