SU1213493A1 - Device for reception and inversed coding of information - Google Patents

Abstract

The invention relates to telecommunications and can be used in recovering information encoded with a perforated code. The invention makes it possible to increase the speed of the device due to the fact that the restoration is performed by a recurrent method. The device contains a switch, keys, registers, delay blocks, block adders, registers, modulo two block units, counters, control block and. switch, Adder block contains modulo-two adders and NOT elements. The control unit contains the element of the permanent memory, the elements of the comparison, the elements of AND, the encoder and the pulse shaper. 1 hp f-ly. 3 il. ts3 00 4 QO 00

Description

The invention relates to telecommunications and can be used. control systems of the transmitted information when recovering information encoded by a convolutional perforated code.

The purpose of the invention is to increase the speed of the device.

FIG. 1 shows a block diagram of a device for receiving and re-encoding information; in fig. 2 - functional block diagram adders (calculator); in fig. 3 - the same, control unit.

A device for receiving and re-encoding information (Fig. 1) contains a switch 1, keys

2 and 3, registers 4 and 5 blocks 6 and 7 delays, block 8 adders (calculator), registers 9 and 10, blocks 11-14 modulo-two adders, counters 15 and 16, control block 17 and switch 18.

Block 8 adders (calculator) (Fig. 2) contains adders 19 33 modulo two and the elements NOT 34 - 37.

The control unit 17 (Fig. 3) contains the permanent memory element 38, the comparison elements 39 and 40, the AND elements 41-43, the encoder 44 and the imaging unit 45 a pulser.

The device works in the following way.

Switch 1 receives an input signal representing a sequence of binary code symbols. Switch I divides the input sequence of characters into two sequences Sj and Si corresponding to two generator polynomials of the convolutional code, taking into account the perforation rule (puncturing or erasing the characters chosen for this perforated convolutional code. The index i indicates the sequence number of the time interval in which is the symbol Si, j. At the initial time, keys 2 and

3open at time i while registers

4 and 5 are not filled. By filling registers 4 and 5, the contents feed them to calculator 8, which determines the initial setup signals for registers 9 and 10.

The sequence of information symbols is denoted by Caj, where i is the sequence number of the symbol.

Then the code symbol 8;, 1 is defined as

Si, i 1a {-GI (x) a; 0ai.i@ai.3terav-i,

F -s

From the last equation, it follows that if the information symbols a are known. aj.j, as well as the Sj code symbols accepted without error, it is possible to make a recurrent- “

a new equation to determine the information sequence

,, @ a) .e®а1 ,,, ® ® | .5 © 8-, 1. (1) By sequence of code symbols Sj, where, 2,3, ... and

S; r g de, 4.7, ... by composing and solving a system of algebraic equations, it is impossible to determine unambiguously five consecutive information symbols. Five information symbols are conventionally assigned under the assumption that the sixth symbol is known. Since this symbol can have only two values O and 1, then for each of these values

You can define a set of information symbols using the following equations: Oj.i Sj ,, i © a; ai swi, i®Su2 i®Si + 3, i © 5i + 3, i © a; -t ,; , i®-5Ui, .j ,, i © Si, .5, i®Su6.i® @ S, 4T.i®Si., i®SU9, ri, i © Si, i © S, t3, - t®Sj +, - a; ,,;

,,, 6. (, г®®Si, i®S;, i-vai ..

The assumption that ajV, 0 and a -,. 1, we get two sets

a, a, a i, a i “.2, a, 4. h and

t g

H-1 a ,. , but,

Yam

1 + 1 I-1.

but,

initial information symbols, one of which is true.

These equations are solved by modulo-adding two sets of channel symbols in the

calculator 8, the functional diagram of which is shown in FIG. 2

As a result of solving the recurrence equation (1) with two different initial conditions, we obtain

two different informational sequences. The recursion equation is solved on register 9 with feedback through modulo-2 adder block 1I, to which S code symbols are received through delay block 6, from switch 1. At the output of adder block 11, a code sequence is generated, which is fed to register 9. The register 10 and the unit 12 modulo-12 adders are similarly connected, on which the recurrence equation (1) is solved with different initial conditions.

Output code sequences from blocks 11 and 12 of adders are fed to switch 18, as well as to the inputs of blocks 13 and 14 of adders, to which code sequences from registers 9 and 10 and from switch

1 through block 7 delay code symbols S; .. Since the code sequence with registers 9 and 10

on blocks 12 and 14 of adders correspond to the generator polynom GI (X), then with the correct information sequence at the input, the output of one of the blocks I3 and 14 adders will be one-zeros, while at the output of the other in ts and units that indicate for errors.

The outputs of the blocks 13 and 14 of the adders through the counters 15 and 16 errors are connected to, connected to the 17th control. Block

The control performs a comparison with a certain threshold stored in the memory block 38 of the readings ot and JB of the counters 13 and 14, respectively. the results of the comparison are the following signals: g: P; and 11 - control signal to the switch

18dl information from the block of 11 adders, 0 P; p P - control signal to switch 18 for outputting information from block 12 adders, o / P; 11 - control signal to switch 1 and simultaneously open signal, keys

2 and 3 for the time required to fill registers 4 and 5, the prohibition of information.

Switch 1 input code sequence converts into two sequences and S l ,. corresponding to two code polynomials Gj (X) and). Since the sequence S; 1 represents a punched (punctured) code sequence, the output of switch 1 is served with a period equal to the period of the code branch

The beginning of the branch (node synchronization) is established by a sequential shift per clock (or

tact skip) jact grid switch 1 on the control signal of the control block 17.

Thus, in the absence of

errors in channel symbols device, error-free results in: information sequence. If there are even single errors in the channel sequence

Sj due to the fact that the recovery of information is performed by a recurrent method — register 9 with feedback through a block 11 of adders (or 10 and 12, respectively;

There is a consistent accumulation of errors in the meters 15 or 16, which is fixed by the control block 17 17.

Single 1 on channel error.

the sequences will be recorded in counters 15 and 16 as a single error.

25

Claims (2)

1. A device for receiving and re-encoding information comprising a first switch. The information input of which is the input of the device, the first output of the first switch is connected through the first delay unit with the first input of the first block of adders, the second output of the first switch Connected through the second delay unit with the first input of the second block of adders, characterized in that, with the purpose of increasing the speed, keys are entered into it, gistra, counters, control unit, third, fourth, fifth blocks sum-. mators and the second switch, the information inputs of the first and second keys are connected respectively to the first and second outputs of the first switch, the outputs of the first and second keys are connected to the input of the first and second registers, the outputs of the first and second the registers are connected respectively to the first and second / inputs of the third block of adders, the first and second; the outputs of the third block of adders are connected to the first inputs of the third and fourth registers, respectively, the first and second outputs of the third register are connected to the second inputs of the first and second blocks respectively coders adders, the output of the first block of adders connected to the second input of the third register, the third input of the second block of adders and the first information input of the second switch, the first and second outputs of the fourth; the register is connected to the first inputs of the fourth and fifth blocks of adders, respectively, the second inputs of which are connected to the outputs of the first and, respectively. The second delay block, the output of the fourth block of adders is connected to the second input of the fourth register, the third input of the fifth block of adders and the second information input of the second switch, the outputs of the second and fifth blocks of adders are connected via the first and second counters to the first and second inputs of the control block, The first, second, and third outputs of the control unit are connected respectively to the main input of the first switch, the combined control inputs of the first and second keys, and the control input m second switch, the second switch output is output Arrange Properties. 0 2. The device according to p. I, about tl and - the fact that the control unit contains a memory element, 5 comparison elements, AND elements, a cipher and a pulse shaper, the output of the memory element is connected to the first inputs the first and second comparison elements, the first and second outputs of the first comparison element are connected respectively to the first input of the first element AND and the combined first inputs of the second and third elements AND, the first and second outputs of the second comparison element are connected respectively to the combined second inputs of the first and a second AND and second input of the third AND gate, outputs of the first 0 and the third element And are connected respectively to the first and second inputs of the encoder, the output of the second element And connected to the input of the pulse shaper, the second inputs of the first and second comparison elements are respectively the first and second inputs of the control unit, the outputs of the second element And shaped. pulse clock and encoder are 0 with the first, second, and third outputs of the control unit, respectively. five Sa 5 „5i5„ S ,, S ,, ,, 5 „S | Sj, i i ffa cgre m atellA Ha firstkinkv- Nakmochi2iZ mt / lb 1 Fig.Z Ljfj H yi chv- nakmochi Compiled by M. Nikulenkov Editor N. Gunko Tehred S. Migunova Proofreader G. Reshetnik Order 782/58 Circulation 516 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Branch ShSh Patent, Uzhgorod, st. Project, 4