SU1206952A1 - Shaft angle-to-digital converter - Google Patents

Description

the registers are connected respectively to the second, third, fourth and fifth inputs of the key management unit, the first and second outputs of which are connected respectively to the first and second control inputs of the switches, the third output of the key management unit is connected to the integrator control outputs, the fourth output of the key management unit is connected to the key control inputs, the second, third and fourth outputs of the second register are connected respectively to the fourth, fifth and sixth inputs of the control unit by the counting trigger and with responsibly to the second, third and fourth inputs of the counter control unit, the output of which through the gate driver is connected to the second counter input, the first, second and third outputs of the second register are connected respectively to the third, fourth and fifth inputs of the register control unit, outputs of the sine-cosine sensor connected to the inputs; a quadrant code generator, the outputs of which are the outputs of the higher bits of the converter; the output of the first OR element is connected to the seventh. the input of the counting trigger control unit, the first output of the counter is connected to the information input of the bus driver, the output of which is connected to the information input of the first register, the output of which is connected to the control input of the controlled divider, 5keni, the second output of the counter is connected to the sixth input of the register control unit, the third output of the counter is connected to the eighth input of the control unit of the counting trigger, the output of the pulse generator is connected to the second input of the second element I, the input of the converter connected to the second input of the first element I and the control input of the first register; the converter correction input is connected to the sixth input of the key management block, the ninth input of the counting trigger control block, the seventh input of the register control block and the fifth input of the counter control block, the reset input of the converter is connected to the reset input of the counting trigger; the Input Read converter is connected to the reset input of the counting trigger.

to the second input of the first element OR and the control input of the bus driver, the outputs of which are the outputs of the lower bits of the converter, the direct output of the counting trigger is the output of the Ready converter signal.

2. The converter according to claim 1, characterized in that the counter control unit comprises two AND elements and the OR element, the inputs of the first AND element are the first and second inputs of the counter control unit, the first input of the second And element is the third input of the control unit the counter, the second input of the second element AND is connected to the first input of the first element AND, the outputs of the elements AND are connected to the first and second inputs of the OR element, the third input of which is the fourth input of the counter control unit, the fifth input of which is. The second input of the AND element, the output of the OR element, is the output of the counter control unit,

3. The converter according to claim 1, which means that the register control block contains five AND elements, two OR elements and the NOT element, the first input of the register control block is the first input of the first AND element, the output of which is connected to the first input of the first OR element, the output of which is connected to the first input of the second AND element, the output of which is connected to the first input of the second OR element, the output of which is the output of the register control unit, the second input of which is the first input of the third AND element, It is connected to the second input of the second OR element, the third input of the register control unit is the first input of the fourth AND element, the output of which is connected

to the third input of the second element OR, the fourth and fifth inputs of the register control unit are the second inputs of the third and second elements AND, the sixth input of the register control unit is the second input of the fourth element AND, the seventh input of the register control unit is connected to the first input of the fifth element and through and

the element is NOT to the second input of the first element AND, the second input of the second element and is connected to the second input of the register control unit.

4. The converter according to claim 1, characterized in that the control unit of the counting trigger contains four elements AND and two elements SH, the first and second inputs of the control unit of the counting trigger are inputs of the first element AND, the output of which is connected to the first input of the first element OR, the output of which is the output of the counting trigger control unit, the third input of which is the first input of the second element AND, the output of which is connected to the second input of the first OR element, the fourth input of the counting trigger control unit is The first input of the second element is SHS, the first input of the third element I is the fifth input of the control unit for the counting trigger, the sixth input of which is the first input four. the And element, the output of which is connected to the third input of the first element OR, the seventh, eighth and ninth inputs of the control unit of the counting trigger, are the second inputs of the second, fourth, respectively

The invention relates to automation and computing and can be used dp connection of analog information sources with a digital computing device.

The aim of the invention is to enhance the functionality of the converter by determining a code equivalent to the current value of the harmonic period of the reference signal.

FIG. 1 is a block diagram of a shaft angle-to-code converter; in fig. 2 - timing diagrams of the output voltages of the integrators and the counting trigger in the correction mode; in fig. 3 - the same in measurement mode} in FIG. 4 is a block diagram of a key management unit;

and the third element And, the output of the second element OR is connected to the third input of the first element I.

5. The converter according to claim 1, characterized in that the key management unit contains AND elements, NOT element and OR elements, the first input of the key management unit is connected to the first inputs of the first and second And elements, the second input of the key management unit is connected to The first inputs of the third and fourth elements AND, the third input of the key management unit are the first input of the OR element, the fourth and fifth inputs of the key management unit are the second inputs of the first and second AND elements, respectively, the sixth input of the control unit the keys are connected to the second input of the fourth element AND, and through the element NOT to the second input of the third element AND, the output of which is the first output of the key management unit, the second output of which is the output of the SHIII element, the third and fourth output of the key management unit are outputs the second and fourth elements I.

FIG. 5 is a block diagram of a counting trigger control block; in fig. 6 - the same, register control block; in fig. 7 - the same, control unit

counter. I

The converter contains a sine-cosine sensor (ACS) 1, voltage source 2, shaper 3 quadrant codes, keys 4 and 5, switches 6 and .7, integrators 8 and 9, controlled voltage divider 10, inverter P, comparator 12 and 13, the OR element 14, the key management unit 15, the AND element 16, the register 17, the counter trigger control unit 18, the counting trigger 19, the OR element 20, the block

21 register control generator

22 pulses, element And 23, the counter 244 tire driver 25, register

26, counter control unit 27, strobe driver 28, input 29 Record, input 30 Correction, input 31 Reset, input 32 Read, input, 33 Ready.

The key management unit 15 contains elements AND 34-37, NOT 38 and .OR 39.

The counting trigger control block 18 contains AND 40-43 and OR 44 and 45 elements.

The register control unit 21 contains AND 46-50, OR 51 and 52 and NOT 53 elements.

. The counter control unit 27 contains the elements of And 54 and 55 and OR 56.

The Converter operates as follows.

In correction mode, the converter operates in four steps.

Signal from the digital computing device (.CTV) is written to register 17; codes 1, O, O, O and element 16 are open, since trigger 19 is reset to the initial state by the Reset signal or the previous operation mode, thereby starting the first operation step. converter At the same time, the register 26 is signaled by the Write signal from the data bus through the bus driver 25, which is open in this direction with no read signal, the code corresponding to the expected state of divider 10, at which the time constants of the integrators 8 and 9 are equal. the trigger 19 is set to the zero state (using the OR element 20 and the block 18 1 and thereby enables pulses from the generator 22 pulses through the AND 23 element to the counting input of the counter 24. At the beginning of the first step, the block 15 gives a signal; its fourth output, and thus the voltage from the output of voltage source 2, via switches 4 and 5 goes to integrators 8 and 9. On the appearance of a pulse at the first output of counter 24 (which sets the duration of the first step), block 21 causes a shift signal the input of register 17, the unit is shifted to the second output of this register, as a result of which the first step-step of integrating the constant voltage on the integrators 8 and 9 is completed.

By the second step, the block 27, through the gate driver 28, has zeroed the counter 24, to which counting pulses continue to flow from the generator

22. At the same time, unit 15 begins to output a signal to the second output, thereby using switches 6 and 7 of the circuit, integrators 8 and 9, and integrator 11 into the ring, forming an oscillator. At the moment when the output voltage of the integrator 8 passes through zero, the comparator 13 is triggered and the signal through the OR circuit 14 and the block 1B sets the trigger 19 to the state of logical one. This stops the counting of pulses in the counter 24, where a code proportional to the angle of 45 ° accumulates.

At the same time, block 21 outputs a signal to the shift input of register 17 and a single signal is shifted to the third output of register 17, thereby ending the second step.

At the beginning of the third step, the state of the counter 24 and the integrators 8 and 9 does not change until the signal appears Read from the DVR (if it has not been before) and during this signal. In the presence of a signal Reading

the bus driver 25 transmits the code 45 from the outputs of the counter 24 to the data bus of the DVR, which, if there is a ready signal (1, the trigger state 19), receives this

code and remembers it. At the end of the read signal using the OR element 20 and the block 18, the trigger 19 is set to the zero state, VeM through the block 27 itself and the gate driver 28, the counter 24 is zeroed and counting pulses begin to arrive again at its input. At the same time, the integrators 8 and 9 and the inverter P are closed in a ring,

as the signal appears again at the second output of block 15, and the formation of harmonic vibrations continues. At the moment of transition of the output voltage of the integrator 9 through

the zero is triggered by the comparator 12 and the signal through the OR circuit 14 and the block 18 sets the flip-flop 19 to a single state, the signal from the block 21 is fed to the shift input of the register 17 and the single signal is shifted to the fourth output of the register 17, the third step ends.

At the beginning of the fourth step, as well as at the beginning of the third step, the converter stops until the signal disappears Reading from the DVR, with which the code corresponding to the 1/4 period of the harmonic oscillations of the converter is now sent to the DVR. At the end of the read signal using the OR element 20 and the block 18, the trigger 19 is set to the zero state, thereby through the block 27 and the gate driver 28, the counter 24 is zeroed and counting pulses arrive at its input. At the same time, a signal arriving at the zero inputs of integrators 8 and 9 appears at the third output of block 15. A signal appears at the second output of counter 24 (which thus sets the duration of the integrators zeroing interval) trigger 19 is set to unit state by block 18 . This completes the correction mode in the converter.

In the DVR, code 45 is multiplied by the code in the number of counting pulses and divided by the t / 4 code, thus forming a code that does not depend on the harmonic oscillation period of the converter and depends on the equality of the constant integrators. Comparing it with the code corresponding to 45 °., The code of the Kczorr is calculated which must be fed to divisor 10, so that the time constants of the integrators 8 and 9 are equal.

Timing diagrams of the output voltages of the integrators 8 and 9 and the direct output of the trigger 19 in the correction mode are shown in FIG. 2cP 5 and and respectively.

In the operating mode, the converter operates in four steps.

Upon arrival of the signal, the recording from the DVR to the register 17 is recorded at 90 °

. . and 1 II IL11

dy 1 and

 Oh oh oo

a single signal at the first output of register 17, the first step of the converter operation starts. At the same time in the register 26 through the open bus driver 25 is entered the code CDrr. At the end of the signal, Record trigger 19 is set to the zero state (using the element OR 20 and block 18) and

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five

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five

0

five

0

five

The resolution allows the impulses to be fed to the counter 24.

At the beginning of the first step, block 15 sends a signal to its first output, as a result of which signals from the outputs of ACS 1 through switches 6 and 7 arrive at the inputs of integrators 8 and 9. When a signal appears at the first output of counter 24, block 21 sends a signal to the shift input register 17, the single signal shifts from the first output to the second output of register 17, the first step ends with I

At the beginning of the second step, block 27

through the gate driver 28, the counter 24 continues to arrive, to which counting pulses from the generator 22 continue to flow. At the same time, unit 15 starts signaling to the second output, closure using switches 6 and 7, integrators 8 and 9, and inverter 11 into a ring, forming an oscillator . At the moment when the output voltage of one of the integrators 8 and 9 passes through zero, one of the comparators 12 or 13 is triggered and the signal through the OR circuit 14 and the block 18 sets the trigger 19 to one state. In this case, the counting of pulses in the counter 24, where the code K proportional to the angle L is accumulated. At the same time, block 21 inputs a signal to the shift input of the register 1 7 and a single signal shifts to the third output of the register 17, thereby ending the second step.

In the third step, the state of the counter 24 and the integrators 8 and 9 does not change, since nothing is fed to their inputs. The third step continues until the signal is read from the DVR (if it does not appear earlier) and during the duration of the signal. In the presence of a signal Read bus driver 25 transmits the code K from the outputs of the counter 24 to the data bus of the DVR, which, in the presence of the Ready signal, receives this code and stores it. Upon signal departure Reading using the OR element 20 and the counting trigger control unit 18, the trigger 19 is set to the zero state, thereby through the block 27 and the gate driver 28, the counter 24 is zeroed and counting pulses begin to arrive again. Simultaneously through block 21

the signal is fed to the shift input of register 17 and the single signal is shifted to the fourth output of register 17, the third step ends. In the fourth step, the third output of the block 15 is a signal arriving at the zero inputs of the integrators 8 and 9. The appearance of the signal. on the second output of the counter 24 trigger

19 with the help of the block 18 sets-s to one. This ends the operating mode of the converter.

Timing diagrams of the output voltages of the integrators 8 and 9 and the direct output of the trigger 19 in the operating mode are shown in FIG. 3 o, g and c respectively.

FIG 2

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Editor L.Gratilpo

Compiled by V.Podol and Tehred, M. Nagy

Order 8733/58 Circulation: SiB

VNSHSHI USSR State Committee

for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab. D. 4/5

Branch PPP Patent, Uzhgorod, st. Project, 4

7

Proofreader V. But ha

Claims (5)

1. CONVERTER ANGLE OF TURNING THE SHAFT INTO A CODE containing a sine-cosine sensor, the first output of which is connected to the first information input of the first switch and the second output is connected to the first information input of the second switch, the output of which is connected to the information input of the first integrator, the output of which is connected to the second information input of the first switch and the input of the first comparator, the second integrator whose output is connected to the input of the second comparator and through an inverter to the second information input of the second switch, the counting trigger, the direct output of which is connected to the first input of the first element I, the second element I, the output of which is connected to the first input of the counter, the source eg zheniya, a first OR gate, the pulse generator, the first register, characterized in that, in order to expand the functionality of the transducer by defining the code equivalent of the current magnitude of harmonic oscillation period of the reference signal, in two keys, a controlled voltage divider, a quadrant code generator, a second OR element, a key control unit, a counting trigger control unit, a second register, a register control unit, a bus driver, a counter control unit and a strobe driver, the voltage source output is connected to informational ones the key inputs, the output of the first key is connected to the output of the first switch and the information input of the controlled voltage divider, the output of which is connected to the information input of the second integrator , the output of the second key is connected to the information input of the first integrator, the outputs of the comparators are connected to the inputs of the second OR element, the output of which is connected to the first input of the control unit by a counting trigger, the output of which is connected to the information input of a counting trigger, the inverse output of which is connected to the first input of the control unit keys, the first input of the second element I, the first inputs of the control units of the register, the counter and the second input of the control unit of the counter trigger, the direct output of the counter trigger is connected En to the third input of the counting trigger control unit and the second input of the register control unit, the output of which is connected to the information input of the second register, to the control input of which the output of the first element is And, the first, second, third and fourth outputs of the second 1206952 > the register is connected respectively to the second, third, fourth and fifth inputs of the key management unit, the first and second outputs of which are connected respectively to the first and second control inputs of the switches, the third output of the key management unit is connected to the integrator control functions, the fourth output of the key management unit is connected to the inputs control keys, the second, third and fourth outputs of the second register are connected respectively. to the fourth, fifth and sixth inputs of the control unit of the counting trigger and respectively to the second, third and fourth inputs of the counter control unit, the output of which through the gate driver is connected to the second input of the counter, the first, second and third outputs of the second register are connected respectively to the third, fourth and the fifth inputs of the control unit register, the outputs of the sine-cosine sensor connected to the inputs of the quadrant shaper code, the outputs of which are the outputs of the high bits of the converter, the output n the first- · OR gate connected to the seventh. the input of the counting trigger control unit, the first output of the counter is connected to the information input of the bus driver, the output of which is connected to the information input of the first register, the output of which is connected to the control input of the controlled voltage divider, the second output of the counter is connected to the sixth input of the register control unit, the third output of the counter is connected to the eighth input of the control unit of the counting trigger, the output of the pulse generator is connected to the second input of the second element And the input "Record" of the converter Yuchen to the second input of the first element And the control input of the first register, the input "Correction" of the converter is connected to the sixth input of the key management unit, the ninth input of the control unit of the counting trigger, the seventh input of the register control unit and the fifth input of the counter control unit, the input "Reset" of the converter connected to the reset input of the counting trigger, the "Read" input of the converter is connected to the reset input of the counting trigger, 1206952 to the second input of the first element OR and the control input of the bus driver, the outputs of which are the low-order outputs of the converter, the direct output of the counting trigger is the output of the signal "Ready" of the converter. 2, Converter π. 1, characterized in that the counter control unit contains two AND elements and the OR element, the inputs of the first AND element are the first and second inputs of the counter control unit, the first input of the second AND element is the third input of the counter control unit, the second input of the second And element is connected to the first the input of the first element And the outputs of the elements And connected to the first and second inputs of the element OR, the third input of which is the fourth input of the control unit counter, the fifth input of which is the third input of the second element AND , the output of the OR element is the output of the counter control unit. 3. Converter π. 1, cast a y u u and. This is because the register control block contains five AND elements, two OR elements and the NOT element, the first input of the register control block is the first input of the first AND element whose output is connected to the first input of the first OR element, the output of which is connected to the first input of the second element And, the output of which is connected to the first input of the second element OR, the output of which is the output of the control unit register, the second input of which is the first input of the third element And, the output of which is connected to the second input of the second el OR, the third input of the register control unit is the first input of the fourth AND element, the output of which is connected to the third input of the second OR element, the fourth and fifth inputs of the register control unit are the second inputs of the third and second AND elements, respectively, the sixth input of the register control unit is the second the input of the fourth element And, the seventh input of the control unit register is connected to the first input of the fifth element And and through element NOT to the second input of the first element And, the second entrance of the fifth ele ment And connected to the second input control unit register. 4. Converter π. 1, according to the block. control of the counting trigger contains four elements And two elements OR, the first and second inputs of the control unit of the counting trigger are the inputs of the first element AND, the output of which is connected to the first input of the first element OR, the output of which is the output of the control unit counting trigger, the third input of which is the first the input of the second element And, the output of which is connected to the second input of the first element OR, the fourth input of the control unit of the counting trigger is the first input of the second element OR, the first input tert This element AND is the fifth input of the counting trigger control unit, the sixth input of which is the first input of the fourth AND element, the output of which is connected to the third input of the first OR element, the seventh, eighth and ninth inputs of the counting trigger control unit are the second inputs of the second, fourth, respectively I1206952 and the third element And, the output of the second element OR is connected to the third input of the first element I. 5. Converter π. I, characterized in that the key management unit contains four elements AND, the element NOT and the element OR, the first input of the key management unit is connected to the first inputs of the first and second elements AND, the second input of the key management unit is connected to the first inputs of the third and fourth elements And, the third block input. Key management is the first input of the OR element, the fourth and fifth inputs of the key management block are the second inputs of the first and second AND elements, respectively, the sixth input of the key management block is connected to the second th input of the fourth element And through the element NOT to the second input of the third element And, the output of which is the first output of the key management unit, the second output of which is the output of the OR element, the third and fourth output of the key management unit are the outputs of the second and fourth elements, respectively.