SU1202551A1 - Apparatus for capimetric examination - Google Patents

Description

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This invention relates to ophthalmic devices and is intended to assess the condition of the retina.

The drawing shows a block diagram of the proposed device.

The purpose of the invention is to reduce the time to determine the boundaries of the perceptual zone.

The device contains a synchronizer 1, a slow-scan unit 2 consisting of a series-connected addressing counter 3 and a permanent memory device 4, a color kinescope scan unit 5, a color kinescope 6, the control inputs of which are connected to the outputs of the coloring unit 7. The stimulus block 8 contains a pair of coordinate counters.

9i} 0, the outputs of which are connected to the inputs of the logic circuit And 11, Block

12 forming the central fixation point consists of two groups of delay blocks 13 and 14, the outputs of which are connected via pulse shapers 15 and 16 to the input of logic circuit 17. The information input of the plotter 18 and the installation inputs of the coordinate counters 19 and 20 along with the installation inputs of the coordinate counters 9 and

10 are connected to the output of the persistent storage device 4. The inputs of the logic circuit 21 are connected to the outputs of the coordinate counters 9

and 20, and the outputs of the logic circuits. AND 11, I7 and 21 are connected to the inputs of the adder 22, the output of which is connected to the input of the coloring unit 7. The output of delay block 23 is connected to synchronization inputs of coordinate counters 19 and 20, and its input together with the input of the color kinescope scanner 5, the inputs of delay blocks 13 and 14 and the information input of the frequency divider 24 is connected to the first output of the synchronizer 1, the second You: the stroke of which is connected to the counting inputs of the coordinate counters 9, 10, 19 and 20. The first output of the two-position switch 25 is connected to the control input of the frequency divider 24, the second output is via the key 26 to the control input of the plotter 18, and the output of the divider 24 often you are connected to the input of the counter 3 addressing. Block 27 stimuli content20255 2

there is a pair of coordinate counters 19 and 20 and a logic circuit 21.

The device works as follows.

5 Synchronizer 1 generates

a mixture of frame and line sync pulses, ensuring synchronous and common-mode operation of the imaging unit 12 of the central fixation point of the blocks

10 8 and 27 stimuli, color kinescope scanner, color kine-; Osprey 6 and divider 24 frequencies.

Blocks 8 27 stimuli with intrasiru- gogic logic signals of point tests 15 objects whose location is determined by the code N and Nn of the current x coordinates x and y, applied to the installation inputs of the coordinate counters 9 and 10 and 19 and 20 a. “The first device 4 has installed the codes H ,, and K ij of the current coordinates V and the slave test object. The parallel code N goes to the installation inputs of the coordinate meter 9 of the anticipating test object and the installation inputs of the coordinate counter 19 of the slave test object. The installation inputs of the coordinate counter 10 anticipating the test object and the installed inputs of the coordinate counter 20 of the slave test object receive the parallel code Ny coordinates ij. Set up new codes N and I ,. in counters 9

35 and 10 and 19 and 20 are carried out by the horizontal and vertical clock pulses (during the return stroke of the CRT line and field), for which the synchronizing inputs of the specified counters

40, the signals from the first output of synchronizer 1 are synchronized. After the I, and N codes are installed, counters 9 and 0 and J9 and 20 are transferred to the subtraction mode {during the back stroke of a CRT), their counts are nocfyned raster sampling pulses in X and y from the second output of synchronizer I. The logical formation of point test objects, the implementation of 50 is as follows. Since the outputs of the counters 9 and 10 and 19 and 20 are connected to the inputs of the circuits And And 21, the signal of logical 1 is set at their outputs (F F FU signal)

55 only at that moment in time, when logical signals 1 are set at all its inputs. At all outputs Q X I Q

ha i

Q

HP

counts Q X I Q

ha i

Q

HP

Counters 9 and 19 will be set to logical levels 1 after the calculation of N +1 pulses. (After rendering the pulses in the subtraction mode, when the code Nj is preset (all outputs of counters 9 and 19 will be set to logical O levels. Overpulse occurs in reversible counters in subtraction mode, i.e., all outputs are set to level 1). Similarly, at all outputs Q y,, Oy, ..., Oup of counters 10 and 20, logical levels 1 will be set after calculating N (+ 1 sampling pulses by U, and overflow of counters 10 and 20 occurs 1 time per frame (signal F, ), while the overflow of counters 9 and J9 - 1 p a line, but at the same time repeats from line to line -2 times, where is the number of lines in the frame. The pulse signal F of the test object appears when FX and F match (,. Although the installation inputs of counters 9 and 19, The N and Ny codes of the X and the slave test object are set 10 and 20. At the outputs of the AND 11 and 2I blocks, the pulses of the test objects are not simultaneously simultaneously. The logical signal of the slave test object at the output of the AND 21 logic circuit is later relation to the pre-test signal of the test object at the output of the AND 11 circuit due to the presence of: and counters 19 and 20. In these counters, the codes N and AND U are set later as compared to counters 9 and 10, later they are switched to subtraction mode for a time determined by the delay and lowercase and personnel

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sync pulses carried out by the block 23 delay. Thus, at that moment in time, when the counters 19 and 20 are transferred to the subtraction mode, the counters 9 and IO have time for the pulses, and

take extra p

and PM

and about.

their overflow occurs at v hours earlier compared with counters 19 and 20; the distance between the forward and the driven test objects is determined by the delay times.

The central fixation point is formed as follows.

Lowercase and frame sync pulses from the output of the synchronizer 1 are received respectively at the inputs of blocks 13 and 14 of the delay. At the exit of these

2025514

Blocks of sync pulses appear with a delay of half a line and a half of a field, respectively. At the outputs of blocks 15 and 16, short pulses of 5 pulses appear, the duration of which determines the dimensions L x and D t | central fixation point. When the line and frame pulses coincide at the output of the AND 17 circuit, a pulsed signal appears;

10 nal central fixation point. The logical signals of the central fixation point and moving test objects are summed up in the adder 22. In the coloring block 7, the color signals of red R, green G and blue B colors are formed in accordance with the control logic signal of the synthesized image.

The movement of test objects is ensured by changing the Ny and HU code of current coordinates V and and test objects when sequentially polling the memory cells of block 4, in which discrete samples of the trajectory of movement of test objects are recorded. Changing the address of the memory cells of block 4 is provided by the addressing counter 3, the output of which sequentially changes the address code

0 memory cells when the input to the counter is 3 addressing. Changing the speed of movement of test objects is achieved by changing the speed of polling the memory cells of block 4. To change the speed of movement of test objects, a frequency divider 24 is used. A change in the speed of movement is provided by changing the division ratio of the clock pulses,

0 received on the counting input of the block 24 from the first output of the synchronizer 1. The division factor of the counting pulses of the block 24 is set by a code at its control input. For example, when

5, the low level of the signal at the control input of the block 24 sets the division factor K, while the pulses of the output of the block 24 have frequencies F ;, and the mode of fast movement of test objects is set. When high. the level of the signal at the control input of the block 24 sets the division factor K; the output of the block is pulses

0

have a frequency f

Lchin

and set

the mode of slow moving test objects.

When conducting research on the visual system described above

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This method periodically presses the two-position switch 25. For example, in the fast-moving test object mode when the test object is disappearing from the field of view, it presses the switch 25, and a high level signal is set at its first output, which translates the device into mode of slow movement of test objects If the slave test object disappears from the field of the test subject, the subject presses the switch 25, and as a result of the level difference at its second the output key 26 is triggered, which will generate a pulse signal coming to the control Editor V. Ivanova

Compiled by And, Bashlykov

Tehred 3.Paliy Corrector. Kolb

Order 8342/3 Circulation 721 Subscription

VNISHCHSH of the USSR State Committee

for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5

Branch PSh1 Patent, Uzhgorod, st. Project, 4

02551b

The plotter input 18, and the first output of the switch 25, will set a low signal level at which the device will be switched to the fast-moving test object mode. When the test subject slave object disappears or appears in the field of view as a result of switching switch 25 to

10, the output of the key 26 is generated by a pulse signal. It is permissive for fixing on the paper carrier of the plotter I8 the coordinates x and C of the slave test object. Fixed

15 on paper, dots characterize the boundaries of the visual field and retinal areas with functional impairments,

2

Claims (1)

DEVICE FOR CAPIMETRIC RESEARCH, containing a synchronizer, a slow-sweep unit, a color picture tube, the control inputs of which are connected to the output of a color picture-scanner unit and the output of a staining unit, stimulus block, memory block, key, and so on that, in order to reduce the time for determining the boundaries of the perception zone, a second stimulus block, a central fixation point driver, an adder, a delay unit, a frequency divider, a two-position switch, and a memory block are made in the form of graph construction eating, and the first synchronizer output is connected to a frequency divider and a slow-sweep unit connected in series, the output of which is connected to the inputs of the stimulus blocks and the memory block, a color picture tube scan unit, serially connected by a central fixation point former, the first adder input and a coloring block, the first block stimuli and sequentially connected by a delay unit and a second stimulus unit, the second output of the synchronizer is connected to the second inputs of the stimulus units, the outputs of which are connected to the second and third inputs of the adder, and the second input of the memory block is connected to the outputs of the key, the input of which is connected to the first output of the on-off switch, the second output of which is connected to the second input of the frequency divider. .